Aug 2026· International Symposium on VLSI Design and Test· pp. 24-29· 0 citations· 17 references
Abstract
We present a hardware-efficient hybrid spiking neural network (SNN) accelerator for video frame interpolation (VFI) on a Zynq-7020 FPGA SoC (53,200 LUTs, 140 BRAM36K, 5 W or less). A five-layer leaky integrate-and-fire (LIF) convolutional SNN is partitioned across programmable logic (PL) and the ARM processing system (PS): Conv1+LIF1 runs in PL as a pipelined Q15 fixed-point streaming engine at 100 MHz, while four deeper LIF layers and an optical-flow head execute on the ARM Cortex-A9 in mixed float32/int8 precision. The PL kernel processes 86.7 million MACs per frame pair at 1.13 percent LUT and 1.43 percent BRAM utilisation, achieving 2.43 nJ per MAC (DMA-inclusive). A controlled Cython-vs-NumPy benchmark identifies the PS as DDR3-bandwidth-bound (0.99 times speedup), bounding PS-only optimisation gains below 5 percent and motivating a PL layer-migration roadmap. The system delivers 2 times frame-rate VFI at 41.37 dB PSNR (SSIM of 0.989) over 50 test triplets, verified by co-simulation with zero discrepancies. With more than 90 percent fabric headroom, migrating two further layers to PL is projected to exceed 10 frames per minute at under 2 W. To our knowledge this is the first characterised hybrid SNN VFI PS-PL co-design on a low-cost reconfigurable edge SoC.
This work presents a multi-role unified buffer that dynamically reuses seven banks as input, weight, intermediate, score, and output storage that reduces BRAM36 requirements by 56.3%, while buffer-control and bank-reconfiguration logic accounts for 4.3% of the lookup tables and 5.3% of the flip-flops in the full accele...
Wooyoung Park, Sangbo Park, Hyungwon Kim· IEEE Access· 0 citations
Low-cost FPGA SoCs can be limited by DSP availability even when logic remains available. We present an edge-AI operator that co-designs selected-layer logarithmic quantization with a synthesizable shift-and-add datapath and AXI-compatible integration. Across classification, segmentation, and detection, short Log-QAT re...
Chang-Yan Liu, Ming Xiao, Sha-Sha Feng· IEEE International Conferenc...· 0 citations
Neural networks (NNs) for real-time medical image processing in resource-constrained environments benefit from hardware platforms that ensure deterministic timing, low latency, and fine-grained control over computational resources. This work introduces a fully custom and modular hardware framework for implementing full...
Mattia Ricchi, F. Alfonsi, M. Barbieri et al.· Applied Sciences· 0 citations
The 194M-parameter model is implemented on an Alveo U50C FPGA using digital fixed-point arithmetic and on an ARM CPU using sparse integer execution to connect event sparsity to omitted computation and data movement in SymbolicLight V2.