Sep 2026· IEEE International Conference on Application-Specific Systems, Architectures, and Processors· pp. 161-162· 0 citations· 5 references
Abstract
Low-cost FPGA SoCs can be limited by DSP availability even when logic remains available. We present an edge-AI operator that co-designs selected-layer logarithmic quantization with a synthesizable shift-and-add datapath and AXI-compatible integration. Across classification, segmentation, and detection, short Log-QAT retains 99.79-99.94% of matched FP32 task quality. On a Zynq-7020, the 9-tap operator uses 0 DSPs and 358 LUTs, reaches 205.04 MHz, and delivers 2.2996 GOPS/W. Relative to matched DSP-MAC and LUT-multiplier baselines, it improves post-route frequency and energy efficiency while remaining DSP-free. Pynq-Z2 experiments reproduce the expected raw outputs in all 40 board cases. These results establish a reusable, physically validated zero-DSP operator and an initial streamed deployment path without claiming a task-complete accelerator.
FlexXNOR-OD is proposed, a new FPGA-oriented accelerator for real-time object detection that combines channel-group precision assignment with a lane-fusible XNOR processing element that offers a practical path toward precision-scalable, multiplier-light object detection on resource-constrained edge platforms.
Budidha Sriman and D. Sateesh· International Journal of Adv...· 0 citations
This work presents a multi-role unified buffer that dynamically reuses seven banks as input, weight, intermediate, score, and output storage that reduces BRAM36 requirements by 56.3%, while buffer-control and bank-reconfiguration logic accounts for 4.3% of the lookup tables and 5.3% of the flip-flops in the full accele...
Wooyoung Park, Sangbo Park, Hyungwon Kim· IEEE Access· 0 citations
RISC-V processors are now widely available for FPGAs, with most FPGA vendors replacing their proprietary soft-CPU architectures with this instruction-set architecture (ISA). Although contemporary FPGAs are increasingly resource- and feature-rich, a soft processor system---including memory---often occupies a disproporti...
Martin Langhammer, Bogdan Pasca, Gregg Baeckler· 0 citations
Memory-polynomial digital predistortion evaluates a small fixed coefficient set over a sliding input history, so its reduction step is a complex-MAC workload with local reuse, so its reduction step is a complex-MAC workload with local reuse.
