Anil Singh

A Hybrid SNN Accelerator for 2X Video Frame Interpolation on FPGA for High Frame Rate Applications

We present a hardware-efficient hybrid spiking neural network (SNN) accelerator for video frame interpolation (VFI) on a Zynq-7020 FPGA SoC (53,200 LUTs, 140 BRAM36K, 5 W or less). A five-layer leaky integrate-and-fire (LIF) convolutional SNN is partitioned across programmable logic (PL) and the ARM processing system (...

PVT-robust dynamic comparator calibration using time-domain offset extraction and hardware-compiled perceptron inference

Self-Adaptive Neural Calibration of Dynamic Comparators Using Time-Domain Encoding

This work presents a dynamic comparator calibration architecture that works entirely in the digital domain with no analog correction element of any kind. The system is built around a StrongARM latch comparator paired with a 7-bit on-chip timeto-digital converter (TDC). Since comparator offset shifts the switching insta...

Noise-Aware Compilation for Heterogeneous NISQ Hardware: A Cross-Topology Empirical Study

Noisy Intermediate-Scale Quantum (NISQ) processors exhibit substantial heterogeneity in their per-edge twoqubit gate error rates, with current-generation devices showing more than two orders of magnitude variation across their coupling map. An empirical cross-topology study of qubitmapping strategies is presented for f...