Jul 2026· 2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)· pp. 1-5· 0 citations· 15 references
Abstract
The edge detection is a crucial procedure in real-time image processing since it allows you to extract features correctly and comprehend the scene. This paper describes a hardware based Sobel edge detector algorithm based on a 16-directional 5 $\times$ 5 kernel implemented on a Zynq-7000 (xc7z020clg400-3) FPGA with various directional gradients to increase clarity of edges relative to the classic 3 $\times$ 3 technique. The hardware/software co-design approach of the system leverages a high-throughput AXI-DMA streaming interface, with hardware taking the heavy load of computationally demanding tasks. The architecture enables the real-time processing continuously with an initiation interval (II) of 1, and thus, the performance is always high. The processing time of a frame is approximately 9.2 ms is achieved and also the hardware resources optimally utilizing 1370 LUTs and 4 BRAM blocks as compared with existing model. The experimental findings reveal a good performance with a balance of accuracy, speed, and efficiency in real-time embedded vision applications with an SSIM of 0.71 and an AUC of 0.80 with respectable error margins.
In an effort to mitigate processing delays and latency in the traditional edge detection in the vision based systems such as robotics and surveillance platforms, this paper attempts to introduce an FPGA-based 3×3 convolution accelerator. The proposed architecture employs a multiply-accumulate (MAC) unit and fixed-point arithmetic (8-bit) to efficiently and effectively implement convolution operations in hardware. The system design is designed in Verilog HDL and simulated to ensure that the measured performance and hardware utilization metrics have been met. The suggested accelerator has proven to be dependable in edge detection and also exhibits a tangible increase in computational efficiency over the established softwarebased methods. The study therefore seeks to cast a light on the appropriateness of FPGA-based hardware acceleration in realtime image processing in embedded vision systems.
Aysha Pareekutty, R. Megalingam· International Conference on...· 0 citations
Edge detection is a key area within computer vision, and it has become an integral part of various application areas. Edge detection enables the identification of edges, which are critical features in images and represent important attributes that help in extracting key and distinguishing information from the images. The hardware implementation of edge detection must be fast, should use minimal resources, consume less power, and must be adaptable to different image resolutions. This paper implements Sobel edge detection for adaptive image resolution, ranging from a low-resolution image to full high-definition, and uses a modern heterogeneous Field Programmable Gate Array (FPGA) platform, the Ultra96-V2. The results reveal that only 5% of the FPGA on-board resources, including the Look up Tables (LUTs), Flip Flops (FF), Digital Signal Processor (DSP), and Block Memory (BRAM), are utilized for low resolution images, while approximately 23% of the onboard resources are consumed for high resolution images. This demonstrates that the increase in resource utilization when transitioning from low resolution to high resolution images is less than 20%. Additionally, the power dissipation is approximately 2 W for the highest resolution, and the maximum operational frequency is recorded at 136 MHz for high resolution and 166 MHz for low resolution images, showing only 18% decrease in the frequency. The proposed architecture achieves sub-linear resource scaling, with less than 20% increase in resource utilization and less than 20% reduction in speed and power when handling a 56-fold increase in pixel count, leveraging the advantages of modern heterogeneous FPGA architecture. Consequently, the adaptive resolution capability combined with low resource scaling makes the proposed design particularly suitable for real-time edge detection applications demanding high-quality image processing.
Image scaling serves as a critical performance bottleneck in real-time video pipelines powering multi-resolution embedded display systems. The design integrates a dual ping-pong line buffer architecture to deliver four pixels per clock cycle, paired with a digital differential analyzer (DDA) for precise sub-pixel coordinate generation. A four-stage pipelined interpolation core optimized for Xilinx Digital Signal Processing 48 (DSP48) slices achieves one-pixel-per-cycle throughput with only six cycles of end-to-end latency. Hardware-software co-verification conducted on ModelSim SE-64 demonstrates perfect reconstruction of constant-color images and 25.8 dB Peak Signal-to-Noise Ratio (PSNR) for gradient images at 4x4 identity scaling. Resource estimates for a Xilinx Artix-7 XC7A35T indicate the design occupies merely 3.8% of available Look-Up Tables (LUTs) and 6.7% of DSP48 slices, making it exceptionally suitable for low-power embedded applications.
Sirui Wang· Computers and artificial int...· 0 citations
This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimation. The localization model is trained and evaluated offline with experimental data from the four-photodiode VLP system reported in the reference work, whereas the SDFT and MLP FPGA blocks are validated separately on a physical Visible Light Communication (VLC) hardware platform. Therefore, the reported 1–2 mm spatial accuracy belongs to the offline reference dataset and model, whereas the FPGA results quantify module latency, numerical fidelity, implementation resources, and tool-estimated power, not physical end-to-end coordinate accuracy. The design was implemented on a AMD Xilinx Zynq-7000 (xa7z020clg484-1Q) SoC FPGA device and operated at 100 MHz. The SDFT block requires 61,655 clock cycles, corresponding to 616.55 μs, while the MLP variants require between 607 and 6612 clock cycles, corresponding to 6.07 μs and 66.12 μs, respectively. All MLP implementations reproduce the offline software reference with HW/SW MSE values on the order of 10−6. The resulting blocks and the reported first HLS integration estimates establish an implementation path while identifying the acquisition, synchronization, and multi-tone validation work still required for a complete receiver.
Randy Lozada Domínguez, Aran White, Jianming Tang et al.· Electronics· 0 citations
Automated Optical Inspection (AOI) systems in industrial production require high-performance front-end image preprocessing hardware with stringent demands for real-time processing, low power consumption, high-fidelity denoising, and limited resources of embedded Field-Programmable Gate Array (FPGA) platforms. Bilateral filtering is a good edge-preserving denoising method, but its data-dependent range Gaussian kernel requires either expensive multi-stage exponential pipelines or large look-up tables, which introduce too much Digital Signal Processor (DSP) and look-up table (LUT) overhead for resource-constrained applications. A piecewise approximate bilateral filter structure is proposed and realised on the Xilinx Zynq XC7Z020 System-on-Chip (SoC) in this paper. A K=16 piecewise-linear approximation of the Gaussian range kernel has been used to avoid exponential evaluation hardware and reduced coefficient storage by a factor of 32. A fully pipelined 5×5 sliding-window architecture operates at 200MHz and can deliver a throughput of 200 Mpixels/s to meet the 1080P@60Hz demand with a margin. Experimental results on the XC7Z020 show a 9.8% and 70.5% reduction in LUT and DSP utilisation, respectively, compared with the conventional bilateral filter baseline, and a measured on-chip power of 0.13W was achieved. The denoising quality of the ten industrial Printed Circuit Board (PCB) test images with additive Gaussian noise is still within 0.28 dB Peak Signal-to-Noise Ratio (PSNR) and 0.003 Structural Similarity Index Measure (SSIM) of the original bilateral filter, so it is perceptually lossless. Design a practical and high-efficiency hardware solution for AOI image pre-processing on resource-constrained embedded platforms.
Unknown authors· European Conference on Elect...· 0 citations
Convolutional neural networks (CNNs) achieve strong accuracy in object detection, but their heavy computation and memory demands make them difficult to run on embedded and mobile hardware. This work proposes a combined hardware-andalgorithm design that pairs a carefully regularized binarized neural network (BNN) with a compact, variable-precision FPGA processor. A new building block called DenseToRes is introduced to reduce the accuracy loss usually caused by aggressive 1-bit quantization. The supporting processor stores the entire trained network in on-chip memory instead of external DRAM and performs its multiplyaccumulate (MAC) operations using an XNOR-based processing element that can flexibly handle 1-, 2-, 4- and 8-bit operand widths from one shared gate array. Implemented on a Xilinx FPGA, the design achieves real-time performance of 64.51 frames per second with 64.92% mean average precision (mAP) on the PASCAL VOC dataset, while consuming only 6.58 W. The results show that jointly optimizing network structure and hardware precision can enable accurate, real-time object detection without relying on off-chip memory.
M. Kanthi, Ragala Karthik· International Journal of AI...· 0 citations
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