FPGA-Based Implementation and Simulation of a 3×3 Convolution Accelerator for Edge Detection

Abstract

In an effort to mitigate processing delays and latency in the traditional edge detection in the vision based systems such as robotics and surveillance platforms, this paper attempts to introduce an FPGA-based 3×3 convolution accelerator. The proposed architecture employs a multiply-accumulate (MAC) unit and fixed-point arithmetic (8-bit) to efficiently and effectively implement convolution operations in hardware. The system design is designed in Verilog HDL and simulated to ensure that the measured performance and hardware utilization metrics have been met. The suggested accelerator has proven to be dependable in edge detection and also exhibits a tangible increase in computational efficiency over the established softwarebased methods. The study therefore seeks to cast a light on the appropriateness of FPGA-based hardware acceleration in realtime image processing in embedded vision systems.