Design and implementation of a high-throughput piecewise approximate bilateral filter on FPGA for automated optical inspection systems

Abstract

Automated Optical Inspection (AOI) systems in industrial production require high-performance front-end image preprocessing hardware with stringent demands for real-time processing, low power consumption, high-fidelity denoising, and limited resources of embedded Field-Programmable Gate Array (FPGA) platforms. Bilateral filtering is a good edge-preserving denoising method, but its data-dependent range Gaussian kernel requires either expensive multi-stage exponential pipelines or large look-up tables, which introduce too much Digital Signal Processor (DSP) and look-up table (LUT) overhead for resource-constrained applications. A piecewise approximate bilateral filter structure is proposed and realised on the Xilinx Zynq XC7Z020 System-on-Chip (SoC) in this paper. A K=16 piecewise-linear approximation of the Gaussian range kernel has been used to avoid exponential evaluation hardware and reduced coefficient storage by a factor of 32. A fully pipelined 5×5 sliding-window architecture operates at 200MHz and can deliver a throughput of 200 Mpixels/s to meet the 1080P@60Hz demand with a margin. Experimental results on the XC7Z020 show a 9.8% and 70.5% reduction in LUT and DSP utilisation, respectively, compared with the conventional bilateral filter baseline, and a measured on-chip power of 0.13W was achieved. The denoising quality of the ten industrial Printed Circuit Board (PCB) test images with additive Gaussian noise is still within 0.28 dB Peak Signal-to-Noise Ratio (PSNR) and 0.003 Structural Similarity Index Measure (SSIM) of the original bilateral filter, so it is perceptually lossless. Design a practical and high-efficiency hardware solution for AOI image pre-processing on resource-constrained embedded platforms.