An Area-Optimized SRAM-Based CIM Macro with Capacitor-Reused SAR ADC Achieving 2048 GOPS for Neural Network Acceleration
This paper presents a charge-domain analog compute-in-memory (CIM) macro that integrates accumulation and analog-to-digital conversion (ADC) using an unified capacitor architecture. By re-utilizing the same binary-weighted capacitor array for both multiply-and-accumulate (MAC) operations and successive approximation re...