Sep 2026· Proceedings of the 19th ACM International Systems and Storage Conference· pp. 163-163· 0 citations· 1 references
TL;DR
This work proposes an architecture that leverages the inherent die white space of high-port-count switches to add shore arbiters, reducing latency and power for intra-shore traffic at zero area overhead and reduces average end-to-end latency by up to 56%.
Abstract
Deep neural networks and large language models require many tightly-connected GPUs employing tensor, pipeline, data and expert parallelism, generating unprecedented many-to-many traffic across scale-up fabrics (e.g. UALink) [1]. A scale-up switch is simpler than conventional Ethernet switches yet demands an order of magnitude more bandwidth. We propose an architecture that leverages the inherent die white space of high-port-count switches to add shore arbiters, reducing latency and power for intra-shore traffic at zero area overhead. At full injection rate and local traffic, the architecture reduces average end-to-end latency by up to 56%.
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