FPGA-Based Asynchronous FIFO Design for Cross-Clock Domain Data Transmission
TL;DR
Results show that the proposed FIFO correctly performs read and write operations, preserves data integrity, and generates accurate full and empty flags under normal and boundary conditions, and is suitable for reliable communication between independent clock domains in digital systems.
Abstract
For modern digital systems with multiple clock domains, asynchronous First In First Out (FIFO) is the predominant solution for reliable cross-domain data transfer. The two problems of the old design are the risk of metastability in multi-bit pointer synchronisation and incorrect generation of empty/full flags. If only one is used, there will be a loss of data, transmission failure, or system instability. This paper presents a configurable asynchronous FIFO implemented in Verilog HDL for Field-Programmable Gate Array (FPGA)-based multi-clock systems. The design uses dual-port RAM, binary-to-Gray-code pointer conversion, two-stage synchronization, and reliable flag detection logic to improve cross-clock data transmission. ModelSim simulation results show that the FIFO correctly performs read and write operations, preserves data integrity, and generates accurate full and empty flags under normal and boundary conditions. Its parameterized structure allows flexible adjustment of data width and FIFO depth without redesigning the architecture. Therefore, the proposed FIFO is suitable for reliable communication between independent clock domains in digital systems.