Low-Power Asynchronous FIFO Based on Idle-Awareness and Hierarchical Update Control

Abstract

Asynchronous First-In First-Out (FIFO) buffers are widely used in multi-clock digital systems to enable reliable data transfer across independent clock domains. Conventional asynchronous FIFO designs mainly focus on functional correctness and clock domain crossing (CDC) reliability, while power efficiency during idle periods is often neglected. This paper presents a low-power asynchronous FIFO architecture based on idle-aware detection and hierarchical update control. A baseline FIFO model is implemented and functionally verified to demonstrate correct data transfer, pointer synchronization, and status flag generation. An idle-state simulation is then constructed to analyze internal switching activity under inactive conditions. The optimized design detects idle conditions from read and write activity and synchronization behavior, then applies selective update control to suppress unnecessary register updates and memory write operations. Simulation results show that the proposed approach reduces redundant switching while maintaining FIFO functionality and CDC reliability. The design provides a practical RTL-level solution for low-power asynchronous FIFO implementation.