Jul 2026· ACM Transactions on Design Automation of Electronic Systems· 0 citations· 11 references
TL;DR
This paper develops two LAC search actions specialized in critical path shortening and area reduction, respectively, and shows that compared to a state-of-the-art area-driven method, this framework further reduces 20% critical path delay with comparable area savings, while being 7.9× faster.
Abstract
Approximate logic synthesis (ALS) is a promising design paradigm for error-resilient applications. It can automatically generate circuits with optimized delay, area, and power at the cost of small errors. Existing methods mainly apply local approximate changes (LACs) to shorten critical paths or reduce area. However, given the large search space of LACs, they struggle to achieve a good trade-off between both objectives. This restricts the timing optimization potential of approximate circuits, particularly since area savings can be reinvested to enhance the drive strength of timing-critical gates. This paper leverages population-based search to explore LACs with positive timing influence in parallel. We develop two LAC search actions specialized in critical path shortening and area reduction, respectively. Guided by a recommender system aware of circuit topology and quality, individuals iteratively execute suitable LAC search actions and refine their explored LAC sets by conflict-free combinations, thus balancing reductions in critical path depth and area. Area savings are then reinvested to enhance the drive strength of timing-critical gates, enabling further timing improvement. Experimental results show that compared to a state-of-the-art area-driven method, our framework further reduces 20.3% critical path delay with comparable area savings, while being 7.9× faster.
SynAct is presented, an adaptive closed-loop LLM reasoning--acting agent that iteratively diagnoses live synthesis reports and reasons over the current circuit state, retrieved tool knowledge, and historical optimization experience to issue targeted commands to improve timing.
Fangzhou Liu, Peiyi Han, Jiawei Liu et al.· 0 citations
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7$\times$ on specific tasks; (2) in system-level design space exploration, top LLMs converge to the optimal configuration with higher reliability than random search, simulated annealing, and Bayesian optimization baselines (5/5 seeds vs. 0-4/5 at the same 24-round budget); (3) strategy-level specification changes remain unsolved for most models. Across the six models, generation and DSE rankings overlap moderately: the strongest code generator is not the fastest architecture optimizer, and the weakest code generator (MiniMax M2.7) still reaches the system optimum on 4 of 5 seeds. On the tasks in FinHardBench, difficulty tracks training data pattern availability more closely than abstraction level. FinHardBench is released as an open-source benchmark.
Weimin Fu, Hejia Zhang, Minghao Shao et al.· 0 citations
LLM-SPICEMixer is introduced, a hybrid synthesis framework that augments genetic netlist generation with IGEL (Inspiration-Guided Evolution with LLMs), an LLM-based proposal operator that improves the median final training reward and the median validation-selected test reward.
Stefan Uhlich, Yagiz Gençer, Andrea Bonetti et al.· 0 citations
ExPLORE is established as the first framework to integrate structured test-time search with LM decoding with transformer-based decoding for analog topology generation, and a practical step toward scaling LLM-driven design automation.
Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties. However, these placement-stage surrogates remain misaligned with downstream routed and timing quality. Prior work reduces this gap with human-designed terms or learned black-box surrogates, but the former requires expert retuning and the latter is difficult to explain, debug, or deploy in analytical placement flows. CoEvoP&R addresses these limitations with a large language model (LLM)-based framework that automatically evolves analytical placement objectives. At each generation, the prompt combines the restricted objective interface, baseline context, and archived prior candidates with routing-related feedback from placement, timing proxy, and routing tools. The LLM proposes readable differentiable objectives, which are embedded and validated in DREAMPlace, evaluated through a timing proxy and an actual router, and stored with their feedback to guide later generations. Across eight ChiP-Bench Nangate45 designs and three seeds, CoEvoP&R reduces post-route routed wirelength and congestion by 16.9% and 36.7%, with gains of 0.70 ns in worst negative slack and a 912 ns reduction in total negative slack magnitude over native DREAMPlace. Across eight ICCAD 2015 Superblue designs, it reduces post-route routed wirelength and congestion by 5.4% and 23.2%. Code is available at https://github.com/FCHXWH823/CoEvoP-R.git.
Ruogu Chen, W. Xiao, Ramesh Karri et al.· arXiv.org· 0 citations
