LLM-SPICEMixer is introduced, a hybrid synthesis framework that augments genetic netlist generation with IGEL (Inspiration-Guided Evolution with LLMs), an LLM-based proposal operator that improves the median final training reward and the median validation-selected test reward.
Abstract
Analog circuit topology synthesis remains challenging because useful designs occupy a tiny fraction of a combinatorial search space, and small structural changes can induce highly nonlinear changes in behavior. Evolutionary algorithms are attractive because they can optimize over discrete circuit topologies using only black-box evaluations, but they often require many SPICE simulations and may converge prematurely. We introduce LLM-SPICEMixer, a hybrid synthesis framework that augments genetic netlist generation with IGEL (Inspiration-Guided Evolution with LLMs), an LLM-based proposal operator. During search, IGEL prompts an LLM with high-performing circuits from the elite set and instructs it to generate a new SPICE netlist, which is then evaluated by SPICE and selected using the same reward mechanism as conventional genetic operators. Thus, the LLM contributes structured topology proposals while simulation remains the source of truth. We evaluate LLM-SPICEMixer on a challenging benchmark task: synthesizing transistor-level circuits that implement a discriminant function for Iris classification. Compared with the genetic framework without LLM guidance, LLM-SPICEMixer improves the median final training reward by 8.4% and the median validation-selected test reward by 8.8%. The best validation-selected circuit achieves 93.3% test accuracy at the nominal tt corner and 85.9% average test accuracy across 17 process, voltage, and temperature corners.
The structural richness of analog integrated circuits poses significant challenges for automatic topology synthesis. Direct transistor-level construction introduces excessive structural details, whereas overly coarse abstraction may obscure critical transistor-level behaviors. This paper addresses the topology synthesis of multistage operational amplifiers (Op-Amps), whose compensation-dependent structural diversity makes automated synthesis particularly challenging. We propose AnalogSyn, a tool for compensation-aware topology synthesis of multistage Op-Amps. By decomposing synthesis into a two-step procedure, AnalogSyn organizes the topology synthesis space in a PZ-guided manner. At the macromodel level, compensation variability is explicitly captured, and infeasible topologies are efficiently pruned using a formal symbolic pole–zero analysis. At the transistor level, each validated macromodel is transformed into multiple transistor-level implementations via intermediate hypergraph representations, enabling structural diversity without blind enumeration. Experimental results demonstrate that AnalogSyn can recover most representative published three-stage Op-Amp topologies in our benchmark and generate previously unreported variants with promising initial pre-layout sizing results. Compared with existing methods, AnalogSyn achieves richer compensation strategy diversity and more efficient, interpretable topology-space exploration.
Mingzhen Li, Bo Li, Bei Yu et al.· ACM Transactions on Design A...· 0 citations
Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present \textbf{NetlistBench}, a structure-verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a deterministic structure-aware oracle. Across six non-thinking LLMs, performance varies substantially with operation-level structural complexity. Simple local edits reach $96\%$--$100\%$ accuracy, while device addition drops to $41\%$--$83\%$ and equivalence judgment to $49\%$--$90\%$. Enabling reasoning substantially improves weaker models but does not eliminate structure-preservation failures, with performance still degrading sharply as the edit horizon increases. NetlistBench identifies netlist reliability as a distinct bottleneck for trustworthy LLM-based circuit design automation.
Jiarui Ma, Jianghan Wang, Yuheng Ma et al.· 0 citations
This paper develops two LAC search actions specialized in critical path shortening and area reduction, respectively, and shows that compared to a state-of-the-art area-driven method, this framework further reduces 20% critical path delay with comparable area savings, while being 7.9× faster.
Xiangfei Hu, Yuyang Ye, Chang Meng et al.· ACM Transactions on Design A...· 0 citations
It is found that neutral framing of behavioural features, reporting the feature value without prescriptive advice, consistently outperforms the prescriptive variants, and that prescriptive feedback steers the median feature value in the advised direction in only 37% of cases despite empirically grounded advice.
V ENDI E VOLVE augments LLM-guided evolutionary search with label-free distributional diversity signals that diagnose population-level collapse and keep semantically distinct programs influential as context for future LLM mutations.
Lei Lei, Atharva Sehgal, Lauren H. Yoon et al.· 0 citations
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7$\times$ on specific tasks; (2) in system-level design space exploration, top LLMs converge to the optimal configuration with higher reliability than random search, simulated annealing, and Bayesian optimization baselines (5/5 seeds vs. 0-4/5 at the same 24-round budget); (3) strategy-level specification changes remain unsolved for most models. Across the six models, generation and DSE rankings overlap moderately: the strongest code generator is not the fastest architecture optimizer, and the weakest code generator (MiniMax M2.7) still reaches the system optimum on 4 of 5 seeds. On the tasks in FinHardBench, difficulty tracks training data pattern availability more closely than abstraction level. FinHardBench is released as an open-source benchmark.
Weimin Fu, Hejia Zhang, Minghao Shao et al.· 0 citations
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