A hardware-implemented adaptive pruning neural network

Abstract

With the rapid growth of artificial intelligence (AI) applications, there is an urgent demand for edge computing hardware with low latency and high energy efficiency. The human brain, a highly parallel and sparsely connected architecture, can efficiently process complex tasks at exceptionally low power consumption, a capability that critically relies on synaptic pruning during neural development. However, current neuromorphic hardware, despite its capability to emulate the human brain for AI tasks, lacks an inherent mechanism to assess the importance of synaptic connections and thus cannot achieve brain-like adaptive synaptic pruning. Here, we demonstrate an adaptive pruning convolutional neural network (APCNN) based on Si-based ferroelectric ambipolar field-effect transistor (Fe-AmFET) crossbar arrays. The reconfigurable ambipolar transport in the Si Fe-AmFET memories enables a single device to implement both positive and negative synaptic weights while intrinsically evaluating connection importance, thereby enabling the crossbar arrays to perform multiply-accumulate (MAC) operations, nonvolatile weight storage, and in situ kernel pruning within the network. Our studies indicate that the network achieves an ultrahigh kernel pruning ratio of 89.58% with negligible accuracy degradation on the Fashion-MNIST dataset, while reducing inference parameters, MAC operations, and core power consumption (including the array and readout circuits) by 92.2%, 97.5%, and 92.4%, respectively.