GPU and RISC-V acceleration for neuromorphic computing based on spiking neural networks: taxonomy, comparison, and open challenges

Abstract

Neuromorphic computing has emerged as an event-driven, energy-efficient paradigm for brain-like information processing. Unlike conventional architectures, it unifies memory and computation to mitigate the von Neumann bottleneck, and it typically relies on spiking neural networks (SNNs) as its computational model. As SNNs grow in structure and scale, their hardware acceleration becomes increasingly important for performance and power efficiency. Among the available platforms, graphics processing units (GPUs) and the open-standard RISC-V instruction set occupy a distinctive position: both remain fully software-programmable, yet they sit at opposite ends of the throughput-versus-efficiency spectrum, which makes their joint study particularly informative for neuromorphic system design. This survey reviews 71 studies published between 2015 and 2025 (45 GPU-based and 26 RISC-V-based) and organizes them into a taxonomy that classifies GPU works into simulation frameworks, training-acceleration techniques, large-scale and multi-GPU simulation, and application deployments, and RISC-V works into instruction-set extensions and tightly-coupled cores, accelerator system-on-chips, programmable neuromorphic processors, and edge deployments. For each study, we extract the software frameworks, learning methods, SNN architectural features, network scale, power and energy, speedup, memory use, runtime, and throughput, and we consolidate the comparable metrics to expose the order-of-magnitude separation between the two platforms in operating power and supported network size. A coverage analysis of the corpus shows that the two communities report largely disjoint metric sets (GPU studies emphasize runtime and speedup, RISC-V studies emphasize power and latency), which we identify as the structural reason a fair head-to-head comparison is currently infeasible; and we note that the efficiency advantage of dedicated neuromorphic chips, used here as the baseline, stems substantially from near- and in-memory organization that itself carries area and energy costs. Building on the gaps identified across the corpus, the survey outlines research directions for next-generation GPU and RISC-V accelerators, including heterogeneous workload partitioning, standardized benchmarking, and integration with emerging in-memory technologies.