DRL-Enabled Polymorphic Acceleration Framework for Flexible and Energy-Efficient Hybrid-Float Deep Learning Inference in Mobile Computing

Abstract

Hybrid-float quantization has emerged as a promising solution for efficient deep neural network inference on mobile platforms, but its practical deployment is still limited by three challenges: compute–transmission imbalance, rapidly growing mapping complexity, and the tradeoff between intermediate-data movement and hardware cost under tight memory constraints. To address these issues, we propose a DRL-enabled polymorphic acceleration framework for hybrid-float inference in mobile computing. The framework integrates three tightly coupled modules: a Graph Builder that constructs a compute–transmission-aware parameterized DAG to expose workload imbalance, a ScaleCore Designer that provides a retargetable hybrid-float hardware template with flexible low-bit floating-point support and a three-level memory hierarchy, and a DRL Scheduler that jointly optimizes deployment and hardware-parallelism decisions under feasibility constraints and normalized multi-objective costs. Experiments on three FPGA platforms across complex CNNs and Bert show that the proposed framework achieves 16.36%–20.25% lower EPF or 19.92%–25.44% higher energy efficiency than state-of-the-art accelerators. These results demonstrate a practical path toward flexible, energy-efficient, and scalable hybrid-float deployment for future mobile intelligence systems.