edge computing

Memory and chaos in a physics-constrained relaxation substrate: phase diagram, multi-timescale forgetting, and disturbance robustness

Reservoir computing exploits the fading-memory dynamics of a physical substrate, yet the memory–chaos trade-off is usually studied on abstract recurrent networks with hand-tuned leak rates. We characterize a physics-constrained relaxation substrate inspired by Si3N4 shallow-trap charge storage: N units with a log-norma...

What Sets the Neural Resting Spectrum - Spectral computation from screened pair interactions

A resting cortical spectrum contains a narrow alpha peak, a weaker and narrow beta peak, and a broad component with no resolvable peak above them. Mechanistic accounts locate each rhythm in a time — a loop transit, or the decay of perisomatic inhibition — so one loop delivers one band, a second band needs a second mech...

Evaluating edge-enabled smart waste management in smart cities: A design-oriented KVI/KPI framework

Results indicate that a split-service edge architecture offers a plausible pathway toward operational efficiency, sustainability, and public value, with wider outcomes to be confirmed through longitudinal KPI-to-KVI assessment.

The Ladder of Rules F: Topological Dynamics of Rule Evolution- Condensation, Fragmentation, and Reconnection

Structural openness endows an adaptive system with the ability to modify itsown constraints, but the evolution of a rule space is not disorderly change; it isgoverned by three basic topological operators that shape its geometric skeleton:rule condensation projects multiple low-level rules into a single high-level metar...

Exact certificates for r(n) = e(n), n = 9–21: regular triangle unions

Version 6 (Augustus 2026) adds r(21) = e(21) = 231, closing the hardest rung to date after a five-day resistance documented in CHANGELOG_v6.md; the pattern now holds for thirteen consecutive values. -- Version 5 (August 2026) adds r(19) = 207 and r(20) = 220, extending r(n) = e(n) = U(n) to twelve consecutive values; t...

FedMCP++: Integrating Modular Expert Heads with Prototype-Guided Contrastive Distillation for Wireless Personalized Federated Learning

FedMCP++, a modular and communication-efficient personalized FL framework in which every client owns a complete private model—a lightweight convolutional backbone with a private expert head—and collaboration is carried out entirely through knowledge exchange rather than parameter exchange, is introduced.

Active reconfigurable intelligent surface-aided wireless powered edge computing: Joint resource allocation for User-Edge energy minimization

HE-FR: A High-Efficiency Fault-Resilient Framework for Stuck-at-Faults Mitigation in ReRAM-Based In-Memory Computing

ReRAM-based in-memory computing (IMC) architectures enable efficient neural-network inference on edge devices, due to their high density and non-volatility. However, ReRAM is prone to the stuck-at faults (SAFs) which would distort weight mappings and reduce model accuracy substantially. To tackle this problem, a high-e...

Next-Generation AI-Driven Digital Twin Framework for Market Volatility Warning and Risk Detection in Global Logistics Supply Chains

Serving as catalysts for real-time insight, predictive intelligence, and autonomous decision-making, digital twin (DT) systems are driving transformation in industrial domains. In global logistics supply chains, the coupling of DTs with AI/ML, edge computing, and 5G/6G connectivity offers powerful capabilities for mark...

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC)...

PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI

We present PROTEUS, an 18 mm2 programmable general-purpose digital compute-in-memory (GP-DCIM) accelerator integrating 4 Mb resistive random access memory (RRAM) and 2.6 Mb tensor static random access memory (SRAM) with a 32-bit hierarchical DCIM instruction set architecture (ISA). PROTEUS features fine-grained 1-D mat...

Tcm: A High-Precision Lossy Compression Algorithm for Time Series Data With Flexible Queue-Value Dynamic Grouping

Piecewise linear approximation (PLA) is pivotal for compressing time-series data under stringent error constraints. However, conventional PLA methods often struggle to reconcile the inherent conflict between aggressive compression ratios (CRs) and the preservation of complex local trends. In this article, we propose Tc...