Lattice: Enabling Scalable Enclaves for Commercial RISC-V Platforms

Abstract

Trusted Execution Environments (TEEs) have been extensively adopted to facilitate various security-critical applications. However, in stark contrast to well-established TEE technologies such as Intel SGX, AMD SEV, and ARM TrustZone, the adoption within the emerging RISC-V architecture has seen limited traction. Specifically, existing TEE implementations on current commercial RISC-V hardware face two primary constraints. On the one hand, most approaches rely on specific hardware extensions or software firmware, hindering their practicality on real platforms. On the other hand, the intrinsic limits of RISC-V’s Physical Memory Protection (PMP) registers, a key hardware mechanism to achieve memory isolation, have significantly restricted the scalability of these designs. To address the above limitations, in this paper, we introduce Lattice, a novel RISC-V TEE framework that enables scalable enclaves on commercial RISC-V platforms with a minimal Trusted Computing Base (TCB). Firstly, for enhanced compatibility and portability, Lattice does not rely on any additional hardware extensions and proposes a non-intrusive Secure Monitor (SM) design for the underlying firmware. Secondly, to fully utilize the system’s available memory, Lattice leverages the Dynamic Physical Memory Permission (DPMP) design to enable the execution of enclaves with non-contiguous physical memory, and decouples the management of enclaves to minimize the size of the TCB. Finally, we evaluate the performance of Lattice under various workloads, including file system I/O, databases, web servers, large language models (LLMs), and different system loads. The experimental results indicate that Lattice achieves performance comparable to other TEE systems.