Design And Implementation Of An XNOR-Based Variable-Precision Object Detection Accelerator For Real-Time Edge AI Applications
TL;DR
A hardware-efficient object detection accelerator based on XNOR-driven variable-precision computation for real-time edge artificial intelligence that reduces arithmetic complexity, memory bandwidth, and power consumption while supporting scalable real-time object detection on FPGA-based edge platforms.
Abstract
This paper presents a hardware-efficient object detection accelerator based on XNOR-driven variable-precision computation for real-time edge artificial intelligence. The proposed network combines DenseToRes and transition layers to preserve feature information under aggressive quantization. Binary convolution is executed through XNOR and population-count operations, replacing most multiplier-based multiply-accumulate units. To maintain detection accuracy, the architecture supports 1-bit, 2-bit, and 8-bit modes so that sensitive layers can use higher precision while deeper layers operate at reduced precision. A parallel array of 64 processing elements performs multiple output-channel computations concurrently using an output-stationary dataflow. The accelerator integrates on-chip feature and weight memories, data-fetch units, batch normalization, RPReLU activation, quantization, pooling, and lightweight control logic. AXI-based interfacing enables integration with an embedded processing system and external memory. The resulting architecture reduces arithmetic complexity, memory bandwidth, and power consumption while supporting scalable real-time object detection on FPGA-based edge platforms.