An Almost Accurate Sum of Absolute Differences Architecture for FPGAs

Abstract

This work presents an almost accurate sum of absolute differences (SADs) architecture that integrates absolute value computation into the first level of the adder tree by exploiting unused lookup table (LUT) inputs, while also introducing a structured carry generation and propagation mechanism across the adder-tree levels, with cross-platform validation on Xilinx and Altera FPGAs. The design achieves a maximum error of one and a mean absolute error (MAE) of 0.25, independent of block size, with diminishing relative error for larger blocks. FPGA implementation results show average LUT reductions of 14.5% on Xilinx and 23.6% on Altera FPGA platforms compared to the least LUT-consuming accurate baseline, while achieving a superior accuracy–area trade-off relative to existing approximate SAD designs. Evaluation in the high efficiency video coding (HEVC) encoder under worst-case conditions shows negligible rate–distortion degradation.