A Power-Aware Verification Architecture for SAR ADC using SystemVerilog Real Number Modeling and Low-Power Techniques

Abstract

This paper presents a power-aware verification architecture for a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), built using SystemVerilog Real Number Modeling (RNM) within a Universal Verification Methodology (UVM) testbench. Unlike conventional functional-only verification flows, the proposed architecture jointly verifies conversion correctness and quantifies the energy impact of a power-gating low-power technique applied to the SAR ADC core. Analog signals such as reference and input voltages are modeled using SystemVerilog real datatypes, allowing fast, event-driven simulation without the overhead of full analog/mixed-signal simulation. A power-gated design is compared against an ungated base-paper implementation using an active-cycle-based savings metric, Savings (%) = (1 − Active Cycles ÷ Total Cycles) × 100. Simulation results show that the power-gated design achieves substantial reductions in active cycles relative to the ungated baseline, with representative sweeps showing energy savings in the range of 56%, while preserving functional equivalence in the converted digital output.