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K. Rajasekhar

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Open access Sep 2026

A Power-Aware Verification Architecture for SAR ADC using SystemVerilog Real Number Modeling and Low-Power Techniques

This paper presents a power-aware verification architecture for a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), built using SystemVerilog Real Number Modeling (RNM) within a Universal Verification Methodology (UVM) testbench. Unlike conventional functional-only verification flows, the propo...

Gonthina Sudeepthi, K. Rajasekhar · 0 citations

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