MemMax: Memory-Parallel FPGA Optimization for Bandwidth-Bound IoT Image Processing

Dorado: Scaling SmartNIC Session Tables on Commodity DDRs

Dorado is a novel design that scales SmartNIC session tables entirely on inexpensive DDR modules and uses three new techniques that extract commodity DDR performance by restructuring session table layout, decomposing processing pipelines to reduce locking, and scheduling memory accesses to minimize stalls.

On Design Principles for Efficient Heterogeneous DRAM-PIM-GPU Systems

Three fundamental design principles are revealed that provide design-space guidance for architects designing the next generation of memory-accelerated LLM systems.

Asynchronous Co-Execution of PyTorch on Zynq-7000: FPGA Matrix Delegation and PS–PL Overlap for End-to-End Inference Throughput

A systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted.

FabricPerf: Measuring NIC-less Scale-Up Network through GPU Communication Kernel Profiling

The rapid growth of distributed machine learning systems shifts ML networks from the CPU/GPU-NIC to GPU-Fabrics architectures, creating an emerging need to measure and optimize NIC-less Scale-up networks. Yet, the disappearance of NICs removes key observability points and leaves existing measurement tools largely limited to coarse, application-layer telemetry. We present FabricPerf, a Scale-up network measurement toolkit that enables fine-grained packet-level timestamping and cross-layer hardware insights. FabricPerf uses a software-hardware co-design that integrates protocol-level probing and GPTP clock synchronization within GPU communication kernels with memory profiling of physical pipelines. We implement FabricPerf for the CUDA/NvLink ecosystem and validate its high precision and low overhead via extensive experiments on H100 and GB200 NVL72. Using FabricPerf, we explore Scale-up network dynamics under varied configurations, with two case studies that reveal critical bottlenecks: (i) channel imbalance in high P99 latency and (ii) memory pipeline inefficiency of ~0% LLC hit-rate. To mitigate these issues, we leverage work-stealing to rebalance channels by 46% and boost throughput by 17.5GB/s, and optimize LLC eviction priorities for memory flows to elevate the LLC read hit-rate to ~35%, yielding 16.07GB/s bandwidth improvement. We believe FabricPerf improves Scale-up network observability, laying a foundation for more complete and efficient network stacks. FabricPerf is open-sourced at github.com/open-neutrino/fabricperf.

Faster than the Speed of BRAM: In-Memory Computing for Next Generation FPGAs

HyST-DNA: Hybrid SRAM-TCAM DNN accelerator with genetic optimization on FPGA

Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments. Conventional compute-centric architectures rely heavily on sequential multiply-accumulate (MAC) operations and frequent off-chip memory access, resulting in high energy consumption, increased latency, and bandwidth bottlenecks. These limitations become more pronounced as neural network models scale in size and complexity. While Ternary Content-Addressable Memory (TCAM) offers an alternative through parallel associative search and constant-time pattern matching, it suffers from excessive power consumption and limited adaptability due to continuous match-line activation. This work proposes a hybrid SRAM-TCAM memory-centric deep neural network (DNN) architecture that integrates three tightly coupled subsystems. First, a two-layer autoencoder with ReLU activations compresses 128-bit input feature vectors to 32-bit latent codes, achieving a compression ratio η=4×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\eta = 4\times $$\end{document} and a 75%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$75\%$$\end{document} BRAM saving. Second an on-chip dual-port BRAM data-locality buffer exploits the compressed representation to eliminate inter-layer off-chip DRAM accesses in the critical inference path. Third, a 256×32\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 32$$\end{document}-bit Ternary Content-Addressable Memory array provides O(1) parallel associative inference. A software-only Genetic Algorithm (GA) with Roulette Wheel Selection (RWS) optimizes TCAM configuration offline prior to FPGA deployment; the converged 8,480-bit chromosome is loaded once at startup and remain static during inference, adding zero dynamic power overhead. The proposed architecture, implemented on a Xilinx Artix-7 FPGA, achieves a 42.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$42.3\%$$\end{document} reduction in power compared to a conventional MAC-based baseline (120.5 mW vs. 208.7 mW), an end-to-end throughput of 108.47 Mops reflecting steady-state pipelined operation at 108.47 MHz (2.42×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2.42\times $$\end{document} speedup), and an inference accuracy of 95.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$95.3\%$$\end{document} – a 1.5%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.5\%$$\end{document} degradation attributable to quantization, evaluated on the benchmark dataset. Power figures are obtained from the Vivado Power Estimator tool (post-implementation) at nominal supply voltage of 1 V. These results demonstrate an efficient and scalable solution for next-generation edge AI inference systems.