Aug 2026· Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication· 0 citations· 52 references
Computer Science
TL;DR
Dorado is a novel design that scales SmartNIC session tables entirely on inexpensive DDR modules and uses three new techniques that extract commodity DDR performance by restructuring session table layout, decomposing processing pipelines to reduce locking, and scheduling memory accesses to minimize stalls.
Abstract
FPGA-based SmartNICs are widely deployed for cloud network function acceleration, but their memory subsystem is under increasing pressure because of large session tables. Conventional wisdom suggests that high packet processing performance relies on advanced memories (e.g., SRAM, HBM), but those are costly to add at cloud scale. Dorado is a novel design that scales SmartNIC session tables entirely on inexpensive DDR modules. At the heart of Dorado are three new techniques that extract commodity DDR performance by restructuring session table layout, decomposing processing pipelines to reduce locking, and scheduling memory accesses to minimize stalls. Our testbed results show that Dorado improves packet processing rates by 33%, even with fewer hardware resources. Further, we have deployed Dorado to millions of servers, processing network traffic from billions of users on a large public cloud for over three years. Our production results show that Dorado can accommodate up to 16M session entries, reduce memory cost by 80%, while enabling 50Mpps line-rate processing.
Memory-bound workloads increasingly dominate modern data-intensive systems, especially in Internet of Things (IoT) pipelines where large volumes of sensor and image data must be processed under strict latency and power constraints, yet CPUs quickly saturate their memory bandwidth even with many cores. FPGAs offer higher sustained bandwidth through customizable datapaths, but naively porting CPU-style C code to high-level synthesis (HLS) often produces severely underutilized hardware. This paper examines how to restructure Cstyle oneAPI SYCL code to unlock FPGA performance using a representative bandwidth-bound task: horizontally flipping PNG images. Starting from a naive HLS design that performs up to 1,480× slower than a Xeon Platinum 8360 CPU, we apply FPGA-centric optimizations including producer-consumer dataflow pipelines, multi-channel DDR parallelism, burst-aligned memory access, and loop unrolling. The optimized design scales to 16 kernels across four DDR channels and outperforms a 40core CPU by nearly 25% on million-image workloads. Our results show that effective memory-bound optimization is essential for achieving competitive FPGA performance and provide practical guidelines for HLS-based FPGA acceleration in data-intensive domains.
Benjamin Mikailenko, R. Rongon, Xiaokun Yang et al.· 2026 International Conferenc...· 0 citations
Cloud-native database systems disaggregate compute and storage resources to improve cost efficiency over traditional monolithic architectures through elasticity and resource pooling. Studies of production data warehouse workloads show that scans (including round trips to storage) account for roughly half of total query runtime. Data lakes and lakehouses amplify this bottleneck through per-query decoding of storage-optimized, compressed file formats such as Parquet. As storage and network bandwidth continue to outpace CPU cost-performance, the CPU cycles spent on decoding increasingly undermine the cloud's cost-efficiency promise. This has led to a wave of specialization across the stack with custom hardware at cloud-vendor scale at the extreme end. We build on this trend and present Oasis, a data-processing SmartNIC that offloads Parquet decoding into the network datapath as a custom hardware accelerator. Oasis features a hardware decoder architecture, software abstraction layer, and end-to-end integration with DuckDB. Our evaluation shows that Oasis hides the cost of Parquet decoding behind the network datapath with minimal overhead, overlapping the scan with the remainder of the query execution. In the best case, this almost doubles DuckDB query throughput.
Jonas Dann, Luca Tagliavini, Gustavo Alonso· 0 citations
StrataCL introduces registration-on-allocation to realize user-buffer direct communication, and designs communication operators with workload-balanced NPU-core partitioning and NPU-driven SDMA offloading to exploit supernode architecture features.
Tian-Cheng Hu, Jin Qin, Yu-Zheng Wang et al.· arXiv.org· 0 citations
Erasure coding provides efficient fault tolerance for large-scale distributed storage systems. However, its data repair process is well-known to be resource-intensive. We find that conventional host-centric, TCP-based repair architectures suffer from severe resource contention. Even in high-bandwidth networks, such interference slows repair operations and degrades service quality. To address this limitation, we propose DPUEC, a novel architecture that fully offloads the entire repair process to a Data Processing Unit (DPU). DPUEC leverages Remote Direct Memory Access (RDMA) to enable kernel-bypass data transfers and utilizes the onboard multi-core processors of DPU for highly parallel decoding. This design establishes a physically isolated data plane for repair traffic, completely bypassing host resources. Our prototype evaluation shows that DPUEC improves repair throughput by 133% - 181% over the state-of-the-art approach across different workloads. More importantly, DPUEC delivers true performance isolation. It eliminates any interference with foreground applications and reduces host CPU utilization on the recovery node to nearly zero.
