A Multi-Core Winograd F(2,3) FPGA Accelerator with Low On-Chip Memory Footprint for VGG16 Convolution

Abstract

Convolutional layers remain one of the main computational bottlenecks in deep neural networks, motivating specialized hardware accelerators for efficient inference. Winogradbased FPGA accelerators reduce the cost of $3 \times 3$ convolutions, but their efficiency depends heavily on how transformed activations and weights are stored, buffered, and delivered to the compute fabric. This paper presents a parameterized multi-core Winograd F(2,3) convolution engine described in Verilog and implemented on a Xilinx ZCU104 FPGA. The design streams the input feature map as narrow row-stripes and caches weights on chip, so that only a few image rows ever reside in block RAM (BRAM); this is the source of its distinctive low-memory profile. Tile-level parallelism across seven compute cores and a broadcast PE array sustain throughput, and a bit-accurate flow based on Pythongenerated VGG16 tensors validates the hardware. On the target FPGA the accelerator reaches 1452 GOPS for the VGG16 conv1 workload at 222 MHz using 16-bit fixed-point arithmetic, while occupying only 3.2% of BRAM, 24% of LUTs, 22.6% of FFs, and $\mathbf{1 0 0 \%}$ of DSPs, at $\mathbf{9, 8 2 ~ W}$. The proposed design therefore offers a strong low-memory operating point for FPGA Winograd acceleration, with the current evaluation focused on the VGG16 conv1 layer.