Author

P. Pereira

3 papers indexed here

We haven’t gathered this author’s papers yet. Follow them and we’ll fetch their work.

Not the right person? Other researchers publish under this name.

Aug 2026

A Multi-Core Winograd F(2,3) FPGA Accelerator with Low On-Chip Memory Footprint for VGG16 Convolution

Convolutional layers remain one of the main computational bottlenecks in deep neural networks, motivating specialized hardware accelerators for efficient inference. Winogradbased FPGA accelerators reduce the cost of $3 \times 3$ convolutions, but their efficiency depends heavily on how transformed activations and weigh...

Thomas Henrique Schmitz, Lorenzo Picinin, P. Pereira et al. · Symposium on Integrated Circ... · 0 citations

Aug 2026

Design of a Flexible Hardware Accelerator for Fast Convolutions Using Row-Stationary Dataflow

The growth of Convolutional Neural Networks (CNNs) in applications such as image classification and real-time object detection is limited by high computational and energy costs, especially for resource-constrained embedded systems. To address this challenge, this paper presents a fully open-source and flexible hardware...

Fabricio Lorenzon, P. Pereira, M. Grellert · Symposium on Integrated Circ... · 0 citations

Open access Sep 2026

Implementation and Evaluation of two 32-Point Butterfly FFT Accelerators in a RISC-V Core

This project integrates two 32-point Fast FourierTransform (FFT) accelerators into the RS5 RISC-V processor, afour-stage pipeline architecture supporting custom instructions.We evaluate two FFT accelerator designs (one with parallelinput/output and another with serial input/output), comparingtheir performance against a...

Bruno Soares Zimmer, P. Pereira, Sergio Bampi et al. · Journal of Integrated Circui... · 0 citations