POSTER: VibeNIC: Toward LLM-driven Agile Development of FPGA SmartNICs

Hardware Design and Security in the Era of Chiplets and LLMs

The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.

FPGAgent: An LLM-Assisted Framework for Autonomous HLS Code Generation and Verification in FPGA Environments

FPGAgent is the first task-specification-to-executable HLS generation framework experimentally validated on a well-established benchmark, and the value of end-to-end validation is demonstrated.

FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?

Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 financial computing tasks, is presented together with three experiments that mirror the real-world FPGA iteration cycle: generating new modules from specifications, tuning system-level configurations across a 6-stage trading pipeline, and adapting existing modules to specification changes. Evaluation of six LLMs on 1530+ experiment rounds yields three findings: (1) models achieve 19-61% functional correctness with timing degradation up to 13.7$\times$ on specific tasks; (2) in system-level design space exploration, top LLMs converge to the optimal configuration with higher reliability than random search, simulated annealing, and Bayesian optimization baselines (5/5 seeds vs. 0-4/5 at the same 24-round budget); (3) strategy-level specification changes remain unsolved for most models. Across the six models, generation and DSE rankings overlap moderately: the strongest code generator is not the fastest architecture optimizer, and the weakest code generator (MiniMax M2.7) still reaches the system optimum on 4 of 5 seeds. On the tasks in FinHardBench, difficulty tracks training data pattern availability more closely than abstraction level. FinHardBench is released as an open-source benchmark.

Rethinking RTL DFT: A Discrete RTL Flow for Parallel DFT Integration

Shift-left DFT methodologies enable early insertion of test logic at the RTL stage, but conventional flows rely on DFT EDA tools to directly insert CODECs, TDRs, MBIST, scan routers, pin multiplexing, boundary scan, and TAP controllers into design RTL, enforcing serial workflows between design and DFT teams, resulting in high tool runtime, license usage, and intrusive design RTL modifications. This paper presents a discrete RTL DFT flow enabling true parallel development at two levels: design-DFT team independence and concurrent wrapper development. Using script-based, modular grey-box abstractions-TestWrap, MemWrap, and IPWrap-the approach decouples DFT integration from functional RTL and continuous tool invocation. A reusable multi-vendor codec library further reduces tool dependency across partitions and projects. Industrial validation across 50 measured design releases demonstrates an average DFT integration turnaround of 3 days, with a worst-case peak of 11 days, while maintaining functional correctness and achieving scalable, cost-efficient shift-left DFT integration in a representative internal deployment.

Automated Generation of RISC-V Extensions with Formal Correctness Guarantees

LithOS Bare-Metal: an unusual path for an RTOS

This paper presents LithOS Bare-Metal (LithOS-BM), a Real-Time Operating System (RTOS) partially compliant with the ARINC 653 APEX standard, designed for small embedded systems where partitioning or virtualization is unnecessary or infeasible, and rapid response times are critical.Integrated Modular Avionics consolidates software functions into shared computing resources, reducing hardware, weight, and power consumption. ARINC 653 defines guidelines for Time and Space Partitioning (TSP), specifying a separation kerneland an APEX API for application software.Originally, LithOS was developed as a guest RTOS for the XtratuM Next Generation hypervisor, which enforces strict TSP within a virtualized environment. However, certain embedded applications do not require complex hypervisor-managed partitioning, particularly when strict timing constraints or hardware limitations prevent virtualization. LithOS-BM addresses this by replacing the hypervisor layer with a custom Board Support Package that interfaces directly with the hardware. This approach maintains ARINC 653 compliance, preemptive task scheduling, and temporal isolation while fully controlling the underlying hardware platform as a standalone RTOS.