Precision-Aware FPGA Implementation of Floating-Point and Posit-Based Derivative Accelerators

Abstract

This article presents a precision-aware FPGA implementation of a derivative computing module using both Register Transfer Level (RTL) and High-Level Synthesis (HLS) design approaches. To evaluate performance, hardware resource utilization, and numerical precision across different arithmetic formats, implementations were developed using FP32, FP24, FP16, and 16-bit Posit arithmetic architectures on the PYNQ-Z2 platform. Experimental results demonstrate the effectiveness of automatic pipelining: the HLS implementation using floatingpoint arithmetic achieves up to 130× speedup over software execution. In comparison, the RTL implementation provides a $42 \times$ speedup. Resource utilization analysis reveals that the computational kernel itself remains lightweight, whereas systemlevel components such as DMA and AXI interfaces account for the majority of the hardware overhead. Among all evaluated formats, the Posit< 16, 1 > implementation achieves a negligible error, along with a speedup of 94×. These results provide valuable insights into the trade-offs among numerical accuracy, hardware overhead, and design methodology in FPGA-based accelerator development.