Thickness Engineering in HfO2-Based Ferroelectrics: A Critical Review of Phase, Switching, Reliability, and Device Trade-Offs

Abstract

HfO2-based ferroelectrics have extended a familiar CMOS high-κ dielectric into a materials platform for nonvolatile memory, low-power logic, and in-memory hardware. This review examines thickness engineering in hafnia, especially Hf0.5Zr0.5O2 (HZO), through the state produced during fabrication, the voltage and time available for switching, and the signal retained during operation. Representative quantitative comparisons retain stack, anneal, electrical state, and endpoint definitions; they show that conditioning and drive voltage can change the apparent thickness trend substantially. Capacitor memory, FeFETs, tunnel junctions, negative-capacitance transistors, and computing devices are compared through architecture-specific read margins and failure criteria. The main unresolved challenge is to isolate thickness effects from coupled process and interface changes and establish reproducible, device-specific operating windows.