Design and Implementation of a High-Speed Quantum Reversible Pipelined Carry Select Adder

Abstract

Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.