Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Abstract

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference generation, sign staging, scale handling, and accumulation remain in CMOS; the subsystem is storage plus readout, not compute-in-memory. We first correct the energy boundary: a reported 28-nm capacitor-powered sensing/read-path value of 1 pJ/bit at 1.2 V is treated as an inclusive local-read quantity, giving a first-order <inline-formula> <tex-math notation="LaTeX">$V^{2}$ </tex-math></inline-formula> projection of 0.293 pJ/bit at 0.65 V, not an array-only measurement. We then derive a conditional criterion for support-circuit energy to exceed the array-cell term. For declared low, central, and high structural assumptions, dominance requires an assumed local-support fraction <inline-formula> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> above 0.430, 0.388, and 0.308, respectively; a decoupled <inline-formula> <tex-math notation="LaTeX">$3\times 3$ </tex-math></inline-formula> sensitivity spans 44.3%–57.3%, with the central case at 49.1%. A public SKY130 reconstruction is retained only as a qualitative topology stress test, not an advanced-node projection. A controlled Bonsai-1.7B sign-inversion experiment conditionally evaluates perplexity sensitivity without mapping imposed faults to MTJ bit-error rate. No fabricated array, extracted layout, measured MTJ energy, physical yield, or token-level speedup is claimed. The result is an assumption-transparent bound showing when read support becomes co-dominant and what evidence is still required for a physical subsystem claim.