Investigation on Hot-Carrier Injection Mechanisms and Reliability Design-Based Strategies in Cryogenically Operated CMOS ROICs for Infrared Focal Plane Arrays

Abstract

Cryogenic operation of CMOS read-out integrated circuits (ROICs) is essential for high-performance infrared focal plane arrays but significantly affects carrier transport and device reliability. This work investigates hot-carrier injection (HCI) mechanisms in 180 nm NMOS transistors operating from room temperature down to 140 K. Electrical characterization and accelerated stress measurements reveal a strong impact of hot-carrier effects at low temperatures, resulting in increased degradation of device characteristics, particularly under channel hot-electron (CHE) and drain avalanche hot carrier (DAHC) stress conditions. Time-to-failure modeling confirms accelerated degradation kinetics while validating conventional substrate-current-based reliability methodologies at cryogenic temperatures. Geometry-based design strategies, notably gate-length optimization, are proposed to mitigate cryogenic HCI effects, enabling an improved performance–reliability trade-off. These results provide key guidelines for design reliability of cryogenic CMOS ROICs for infrared imaging applications.