The proposed DBNN spike sorter achieves high accuracy with extremely low hardware cost and multiplier-free operation, making it suitable for low-power, implantable neural interfaces.
Abstract
Implantable brain-computer interfaces require on-node spike sorting to reduce telemetry bandwidth and power while maintaining reliable neural decoding. This paper presents a hardware-oriented deep binarized neural network (DBNN) spike-sorting system with two binarized hidden layers with 256 neurons and a fixed-point output layer to enable multiplier-free inference dominated by sign-controlled accumulation and bit-wise logic. The proposed classifier operates on compact 16-sample spike waveforms to reduce the implementation cost (16-256-256-3) and achieves a median classification accuracy of 98.7% on both synthetic and in-vivo datasets. An FPGA prototype on a Cyclone V device operates at 50 MHz and requires 528 cycles per spike, corresponding to a 0.01 ms compute latency, while consuming 828 ALMs and 1023 registers with zero DSP blocks. For ASIC feasibility, the DBNN is implemented using FreePDK45-based flow; synthesis in Synopsys Design Compiler indicates an estimated silicon area of 0.014 mm2 and an operating power of 122 nW at 20 kHz under a 1.1 V supply. These results demonstrate that the proposed DBNN spike sorter offers a favorable trade-off between accuracy and implementation cost, supporting low-power, implantable neural interfaces. Overall, the proposed DBNN spike sorter achieves high accuracy (98.7%) with extremely low hardware cost (0.014 mm2, 122 nW at 20 kHz) and multiplier-free operation, making it suitable for low-power, implantable neural interfaces. This paper introduces the first DBNN designed for real-time neural spike sorting, striking an excellent balance between input data size and network complexity.
Implantable neural interfaces require low-power real-time signal processing to remain within strict thermal and bandwidth constraints, motivating lightweight feature extraction methods for on-chip spike sorting. This work presents the Walsh-Hadamard Transform (WHT) as a hardware-efficient feature extraction method for neural spike classification. WHT can be implemented using only adders, subtractors, and registers without coefficient memory. WHT performance is compared against the Compressed Hadamard Transform (CHT) and Principal Component Analysis (PCA), improving mean F1-scores from 55-60% to 70-75% on difficult high-noise datasets and from 90-95% to 95-99% on all other simulated datasets. In addition to improved classification performance, WHT demonstrates greater robustness to noise, downsampling, reduced training size, and distance metric selection, maintaining standard deviations typically below 5%, while CHT and PCA reach up to 10% under high-noise conditions.
Emily L. Yang, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin et al.· 0 citations
Spiking Neural Networks (SNNs) are promising for low-power edge intelligence due to their event-driven computational model. However, their hardware implementation poses challenges in terms of energy efficiency and memory access overhead. This paper presents an SRAM-based near-memory computing neuromorphic core supporting 256 leaky integrateand-fire neurons and 65,536 synapses. Synthesized in 40 nm low-power CMOS, the core occupies 0.3 mm2, operates at 70 MHz, consumes 7.67 mW, and achieves $\mathbf{0 . 6 4} \mu \mathbf{J}$ per inference and 0.22 pJ per synaptic operation. A five-core SNN system reaches 96% accuracy and 11 kFPS throughput on the MNIST dataset. A complete System-on-Chip was fabricated using SkyWater 130 nm CMOS via the eFabless multi-project wafer platform, including a small programmable computing core interfaced with a RISC-V processor via the Wishbone bus as a standard memory-mapped peripheral. This core implements 32 neurons and 8,192 synapses, and occupies 0.33 mm2 within a total chip area of 7 mm2. Firmware was loaded onto the SoC to verify the functionality of the full hardware-software system. Measurement results confirm improved energy efficiency and real-time performance, highlighting the suitability of SRAM-based architectures for ultra-low-power neuromorphic computing at the edge.
Linh Nguyen-Phuong, Chi Hoang Phuong, Anh Ong-Tung et al.· IEEE International Conferenc...· 0 citations
High-density neural interfaces require power-efficient acquisition and on-chip processing for low-latency closed-loop operation. While level-crossing ADCs (LC-ADCs) offer efficient front-end acquisition, their integration with large-scale on-chip spike-sorting remains unexplored. In addition, existing on-chip spike sorters rely on temporal or spatial features alone, or on high-dimensional snippets, limiting the accuracy and efficiency. To address these limitations, this work presents a 128-channel neural digitization and spike-sorting system-on-chip (SoC) in 22-nm FDSOI CMOS, introducing three main novelties. First, a synchronized LC-ADC front-end coupled with pulse-domain spike detection reduces the detection power and area by 15.34% and 37.96% compared to NEO-based approaches with negligible accuracy loss. Second, a spatial spike realignment module corrects noise-induced electrode misalignment, improving the accuracy by 6.83%. Third, a compact spatiotemporal feature extractor uses 8 features to improve the accuracy by up to 9.18% while reducing the hardware cost. The chip consumes 1.2 µW and 0.00176 mm2 per channel for recording, and 1.09 µW and 0.0016 mm2 per channel for on-chip spike sorting. These results demonstrate the first large-scale co-integration of a synchronized LC-ADC front-end with hardware-efficient spatiotemporal spike sorting, enabling scalable and low-power neural interfaces.
Yunzhu Chen, Xiaonan Xing, Xiaolin Yang et al.· IEEE Transactions on Biomedi...· 0 citations
This work introduces the first end-to-end neuromorphic spike-encoding and evaluation of the TIMIT dataset and quantifies the pipeline's efficiency with hardware-agnostic metrics based on the quantitative spiking activity.
Valentin Meunier, Amélie Gruel, Pierre Lewden et al.· 0 citations
Spiking Neural Networks (SNNs) provide a power-efficient neuromorphic alternative to traditional artificial neural networks by processing information through discrete temporal events. This paper presents the design and Field-Programmable Gate Array (FPGA) implementation of an inference-only SNN accelerator optimized for MNIST digit classification. To address the physical routing constraints and timing bottlenecks inherent in low-cost devices, we propose an optimized hardware microarchitecture featuring a time-multiplexed 1-bit spike-feeding mechanism governed by a finite state machine (FSM), localized distributed memory for weight storage, and an integer-based Leaky Integrate-and-Fire (LIF) neuron model with register widths selected to prevent overflow. In addition, a multi-cycle pipelined argmax and tie-breaker readout module eliminates the dominant combinational critical path. Implemented on an entry-level AMD Artix-7 FPGA (XC7A200T) using a 784-64-10 network topology, the proposed pipelined architecture increases the maximum operating frequency (Fmax) from 13.3 MHz to 167 MHz. Hardware evaluation demonstrates a sequential processing latency of 82 {\mu}s per image, enabling a 1,000-sample VHDL simulation batch to be completed in 0.082 s. Vivado post-implementation vector-based power analysis estimates the total on-chip power consumption at 0.336 W and the energy efficiency at approximately 36,300 samples per joule. These results demonstrate that the proposed microarchitecture provides a resource-efficient solution for real-time neuromorphic edge inference, provided that the network size remains within the practical limits of time-multiplexed execution.
Recent advances in biologically inspired neural computation have sparked increasing interest in developing hardware-efficient architectures capable of emulating brain-like cognitive abilities like low power consumption and less inference latency. However, significant hardware overhead and spike-processing complexity remain major challenges in FPGA implementations of spiking neural networks. In this work, we propose a sparse spike-aware and weight pruning FPGA architecture based on LIF neurons that minimizes spike activity and synaptic operations through pruning-aware event-driven computation. The proposed sparse spike-aware SNN architecture was evaluated using the Iris dataset. The dataset was divided into 80% training and 20% testing samples. Pre-trained weights obtained from software-level training were deployed onto the FPGA-based LIF classifier. Classification accuracy was computed by comparing predicted output spikes against ground-truth class labels. Experimental results demonstrated that the proposed architecture achieved an overall classification accuracy of 93.3% while maintaining low hardware resource utilization and reduced power consumption. Moreover, the implementation achieves superior energy efficiency, consuming only 3.5 W total on-chip power and utilizing 587 logic cells, confirming its suitability for compact, real-time edge computing neuromorphic applications.
Alishba Masood, M. Khurram· Journal of Low Power Electro...· 0 citations
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