A 128-Channel Level-Crossing-Based Neural Digitization and Spike Sorting SoC With Compact Spatiotemporal Feature Extraction.

Abstract

High-density neural interfaces require power-efficient acquisition and on-chip processing for low-latency closed-loop operation. While level-crossing ADCs (LC-ADCs) offer efficient front-end acquisition, their integration with large-scale on-chip spike-sorting remains unexplored. In addition, existing on-chip spike sorters rely on temporal or spatial features alone, or on high-dimensional snippets, limiting the accuracy and efficiency. To address these limitations, this work presents a 128-channel neural digitization and spike-sorting system-on-chip (SoC) in 22-nm FDSOI CMOS, introducing three main novelties. First, a synchronized LC-ADC front-end coupled with pulse-domain spike detection reduces the detection power and area by 15.34% and 37.96% compared to NEO-based approaches with negligible accuracy loss. Second, a spatial spike realignment module corrects noise-induced electrode misalignment, improving the accuracy by 6.83%. Third, a compact spatiotemporal feature extractor uses 8 features to improve the accuracy by up to 9.18% while reducing the hardware cost. The chip consumes 1.2 µW and 0.00176 mm2 per channel for recording, and 1.09 µW and 0.0016 mm2 per channel for on-chip spike sorting. These results demonstrate the first large-scale co-integration of a synchronized LC-ADC front-end with hardware-efficient spatiotemporal spike sorting, enabling scalable and low-power neural interfaces.