Aug 2026· IEEE Non-Volatile Memory System and Applications Symposium· pp. 1-6· 0 citations· 16 references
Abstract
Hybrid flash storage combines large-capacity highdensity flash memory with high-performance low-density flash memory, providing excellent cost-effectiveness. Existing data placement strategies for hybrid flash storage typically employ hotness-based data migration relying on a twotier architecture. This approach not only overlooks the variations in read retry counts across different reliability stages, but also leads to severe capacity degradation and exacerbated write amplification. To address these issues, we propose RARO, a Reliability-Aware Read performance Optimization scheme for hybrid flash storage. RARO redesigns data placement by leveraging application-level data access patterns and device-level flash reliability. This is achieved by dynamically migrating data based on its retry count and access hotness. Data residing in an unsuitable flash type triggers immediate migration, with higher priority given to data exhibiting both high retry counts and hotness for placement into low-density flash, thereby enabling proactive performance optimization. Furthermore, RARO employs a progressive threetier (SLC-TLC-QLC) management framework to mitigating the capacity loss. The evaluation of RARO, conducted on the FEMUbased emulator, significantly enhances read performance, with IOPS reaching 9.46× to 15.9× of the baseline across different aging stages, while also recovering 57% to 92% of the usable device capacity.
FlashAccel integrates HBF into HBM-based GPUs, providing architectural support to mitigate access latency and introduces an HBF-aware storage management layer together with a programming model to organize persistent data in HBF and coordinate heterogeneous memory resources at the system level.
Xinyu Wang, Yalong Xue, Xiaotian Sun et al.· 1 citation
FLINT is proposed, a workload-driven HBF substrate for capacity-scalable LLM inference that integrates HBF as a memory-capacity tier alongside HBM while addressing three adoption challenges.
Geraldo F. Oliveira, Arash Tavakkol, Xiang-Yu Zhu et al.· 0 citations
Flash memory, characterized by its rapid read and write capabilities and compact size compared to traditional hard disk drives (HDDs), has become a dominant choice for modern storage devices, particularly solid-state drives (SSDs). Despite its advantages, flash memory suffers from device wear caused by repeated write and erase operations, which increases the probability of read errors and ultimately limits SSD lifespan. To enhance SSD reliability and performance without incurring significant resource overhead, prior research has explored data allocation strategies that place frequently accessed data into lower-latency flash locations. However, such schemes typically rely on per-page access counters or LRU-based buffer management, both of which introduce non-negligible metadata maintenance overhead on resource-constrained SSD controllers. This paper introduces a Lightweight Cache Buffer Management (LCBM) strategy that avoids precise frequency tracking altogether. LCBM combines a batch-based first-in-first-out (FIFO) buffer policy with a simple swapping mechanism that dynamically adjusts data placement across the least significant bit (LSB), central significant bit (CSB), and most significant bit (MSB) positions, keeping frequently accessed data in cells with shorter read latency while fully exploiting multi-plane and intra-channel parallelism. Trace-driven simulation shows that, relative to the state-of-the-art FSPDA, LCBM reduces the average read latency by 13.62% and the write response time by 66.81% (and by 16.82% and 64.97%, respectively, over OSPADA), while eliminating the metadata overhead of counter- and LRU-based designs. We further validate LCBM at the system level on the FEMU emulator using both Filebench workloads and real-user traces, where it sustains competitive-to-higher throughput under realistic, long-term deployment scenarios.
Thanks to notable performance and capacity advantages, NVMe SSDs promise an effective cache tier for alleviating the load pressure of back-end storage servers. Compared with DRAM, an NVMe SSD exhibits up to hundreds of times larger capacity but delivers two orders of magnitude smaller bandwidth per gigabyte. This paper reveals that these hardware characteristics challenge fundamental design goals of caches: (1) storing tons of objects in a large-capacity SSD easily induces severe, persistent fragmentation, resulting in low cache space utilization; (2) intensive front-end requests contend for limited SSD bandwidth, causing unpredictable cache lookup latency. To tackle these challenges, this paper presents Gemini. The core of Gemini is heat-informed, group-based object management with a hardware-assisted I/O prioritization mechanism. Specifically, we introduce a tree-based prediction model for agile object grouping and fast reaction to hotspot shift. It provides SSD-friendly, bulk object eviction with a zero-write, remapping-based migration mechanism. In addition, to ensure request performance, we propose a novel I/O model that mitigates bandwidth congestion and prioritizes their processing at the hardware layer. Evaluation results show that Gemini delivers up to 3.8<inline-formula><tex-math notation="LaTeX">${\boldsymbol{\times}}$</tex-math><alternatives><mml:math><mml:mrow><mml:mo mathvariant="bold">×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="cai-ieq1-3711088.gif"/></alternatives></inline-formula> throughput improvement, 2<inline-formula><tex-math notation="LaTeX">${\boldsymbol{\times}}$</tex-math><alternatives><mml:math><mml:mrow><mml:mo mathvariant="bold">×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="cai-ieq2-3711088.gif"/></alternatives></inline-formula> tail latency reduction, and 2.7<inline-formula><tex-math notation="LaTeX">${\boldsymbol{\times}}$</tex-math><alternatives><mml:math><mml:mrow><mml:mo mathvariant="bold">×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="cai-ieq3-3711088.gif"/></alternatives></inline-formula> higher cache space utilization than state-of-the-art caches for both YCSB workloads and production applications.
In-storage computing (ISC) is considered a next-generation memory architecture for its ability to relieve the data bottleneck between the host and the memory. While the required resources of large language models (LLMs) have increased significantly in recent years, the memory density has not scaled accordingly. Recently, several works have studied NAND flash-based processing-in-memory (NAND-PIM) schemes to exploit the high density of the memory. However, they do not address the dataflow/buffer for the intermediate values, so a simple method is to deal with the values in the slow flash memory array. To overcome such a limitation, we propose a high-performance NAND flash-based ISC architecture with enhanced activation buffering. Instead of using the very slow flash memory array for the intermediate values, our architecture buffers the values in a fast DRAM subsystem. This approach effectively handles the high-latency penalties when activations are programmed into slower TLC NAND flash. We also introduce a distributed dataflow approach for the NAND-PIM array. This approach maximizes computational parallelism by employing efficient intra-plane data mapping. The results show that our proposed architecture achieves significant performance improvements, reducing the inference latency by up to 85% compared to the baseline.
Sanghun Shin, Sangyeon Kim, Gisan Ji et al.· 0 citations
Modern computing system heavily depends on the flash-based memory system. Effective cache management is fundamental to improving performance and extending lifespan of flash memory. Traditional page-replacement algorithms, such as LRU, were originally designed for magnetic disks and do not fully deal with the unique characteristics of flash memory, including asymmetric read and write speeds and limited erase operations. This article introduces an enhancement to the Clean First LRU (CFLRU) algorithm, termed Dirty Hot Clean Hot CFLRU (DCH-CFLRU), which provides both clean and dirty pages with a second chance. The proposed solution aims to reduce write counts while upholding a stable hit ratio. Experimental outcomes show that DCH-CFLRU reduces write operation by up to 14% compared to CFLRU through multiple datasets specially in write most cases. The modified algorithm exhibits better overall flash memory performance and extending its lifespan.
Panch Dev Bhatta, S. R. Joshi, A. Saud· Journal of Physical and Life...· 0 citations
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