Automated Digital Logic Circuit Optimization Using Intelligent Systems

Abstract

ABSTRACT In view of the development of semiconductor manufacturing technology to the sub-3nm nodes, traditional Electronic Design Automation (EDA) approaches face challenges when navigating through the huge search space associated with multi-objective optimization in the realm of Power, Performance, and Area (PPA). Classic logic synthesis is based on handcrafted heuristics and deterministic minimization techniques that perform poorly in scalability and often get stuck at the local optimum. This work presents a novel intelligent solution for automatic digital logic circuit optimization using Directed Graph Convolutional Networks (DGCNs) along with Reinforcement Learning (RL). As a result of the representation of And-Inverter Graphs (AIGs) as directed graphs, DGCNs are able to exploit the structural dependencies and predict the timing and power constraints even before the physical mapping takes place. At the same time, the Proximal Policy Optimization (PPO) agent acquires the optimal sequences of algebraic logic operations to optimize the efficiency of PPA. Experimental results conducted on ISCAS-85 benchmark circuits show an average reduction of 13.8% in the number of gates, 11.5% in the critical path delay, and 9.2% in dynamic power in comparison with traditional synthesis passes based on heuristics.