Reinforcement Learning for Optimizing Automated Logic Gates

Abstract

Abstract The optimization of logic gates plays a crucial role in Electronic Design Automation (EDA), typically managed by applying deterministic, rule-based heuristics to And-Inverter Graph (AIG) models of a circuit. As circuit complexity rises to billions of gates, these heuristic methods find it increasingly difficult to avoid local minima and generalize across various designs and technology libraries. This study explores Reinforcement Learning (RL) as a different method for optimizing automated logic gates, where an RL agent acquires the ability to choose and order synthesis transformations like rewriting, refactoring, and balancing operations to reduce metrics such as gate count, delay, and area while adhering to timing constraints. We explore how RL formulations represent logic synthesis as a sequential decision-making challenge, enabling agents to uncover unconventional optimization sequences that surpass static heuristic methods like ABC's resyn2. We investigate how graph-based state representations, such as Graph Convolutional Networks, improve an agent's capacity to generalize over circuit topologies. We finish by addressing major limitations of current RL-driven synthesis methods, such as the need for training data, ability to generalize to new circuit families, and compatibility with existing EDA toolchains.