A framework built on top of Zephyr RTOS that enables secure multitenancy on MCUs that leverages PMP-based hardware memory protection for tenant isolation, dynamically loadable applications via Zephyr’s LLEXT subsystem with mTLS-authenticated connection for post-deployment reconfigurability, and a condition-based publisher-subscriber model that minimises kernel-to-user crossings to preserve real-time behaviour.
Over the past two decades, the complexity of electronic components has significantly increased leading to the widespread adoption of heterogeneous System-on-Chip (SoC) architectures. These SoCs integrate various processing units, such as CPUs, GPUs, and specialized accelerators, to enhance performance and efficiency. However, this integration introduces vulnerabilities, necessitating robust security measures. A popular approach to enhance security in SoCs is the use of Trusted Execution Environments (TEEs). TEEs provide an isolated environment where sensitive tasks are protected from the main operating system and other potential threats. This paper presents SoTTEE, an architecture for TEE that has been developed for use in FPGA-only platforms which do not include ASIC-implemented cores and third-party security mechanisms. SoTTEE is not dependent on the SoC's architecture, Instruction Set Architecture (ISA) or any specific IP mechanism. It leverages SoC heterogeneity to provide strong physical isolation. SoTTEE introduces a bi-level isolation, combining a hardware-based Source of Trust (SoT) with flexible software sanctuaries for enhanced security. We propose a proof of concept implementing the hardware components of SoTTEE to evaluate the performance and pertinence of our architecture.
Simon Baissat-Chavent, Lilian Bossuet, C´edric Killian· ACM Transactions on Reconfig...· 0 citations
Floating point virtualization allows existing, unmodified application binaries to be run using an alternative arithmetic system. Such virtualization is geared to alternative numbers that are “larger” (require more bits) than the IEEE 754 numbers (e.g., 64 bit doubles) they replace. In this work, we approach the challenge of virtualizing with “smaller” numbers (requiring fewer bits), which is of increasing interest given the explosion of low-precision hardware targeting AI. We focus specifically on the ubiquitous x64 architecture through a hardware/software co-design that leverages x64 functionality that currently lays fallow. The design combines (a) instruction traps via lazy FPU abduction, and (b) simplified memory management by tiny value boxing. We also develop an example tiny alternative arithmetic system that allows smaller IEEE 754 numbers, down to 3 bits, with the exact precision able to be specified on a per-value or per-instruction basis at runtime. Our prototype system is evaluated using validation and performance tests based on running NAS and other benchmarks with a range of lower precision numbers.
Kevin Hayes, Peter Dinda· IEEE International Symposium...· 0 citations
Trusted Execution Environments (TEEs) have been extensively adopted to facilitate various security-critical applications. However, in stark contrast to well-established TEE technologies such as Intel SGX, AMD SEV, and ARM TrustZone, the adoption within the emerging RISC-V architecture has seen limited traction. Specifically, existing TEE implementations on current commercial RISC-V hardware face two primary constraints. On the one hand, most approaches rely on specific hardware extensions or software firmware, hindering their practicality on real platforms. On the other hand, the intrinsic limits of RISC-V’s Physical Memory Protection (PMP) registers, a key hardware mechanism to achieve memory isolation, have significantly restricted the scalability of these designs. To address the above limitations, in this paper, we introduce Lattice, a novel RISC-V TEE framework that enables scalable enclaves on commercial RISC-V platforms with a minimal Trusted Computing Base (TCB). Firstly, for enhanced compatibility and portability, Lattice does not rely on any additional hardware extensions and proposes a non-intrusive Secure Monitor (SM) design for the underlying firmware. Secondly, to fully utilize the system’s available memory, Lattice leverages the Dynamic Physical Memory Permission (DPMP) design to enable the execution of enclaves with non-contiguous physical memory, and decouples the management of enclaves to minimize the size of the TCB. Finally, we evaluate the performance of Lattice under various workloads, including file system I/O, databases, web servers, large language models (LLMs), and different system loads. The experimental results indicate that Lattice achieves performance comparable to other TEE systems.
Yu Zhao, Jia-Bei He, Ming-Ru Xu et al.· ACM Transactions on Architec...· 0 citations
This paper presents LithOS Bare-Metal (LithOS-BM), a Real-Time Operating System (RTOS) partially compliant with the ARINC 653 APEX standard, designed for small embedded systems where partitioning or virtualization is unnecessary or infeasible, and rapid response times are critical.Integrated Modular Avionics consolidates software functions into shared computing resources, reducing hardware, weight, and power consumption. ARINC 653 defines guidelines for Time and Space Partitioning (TSP), specifying a separation kerneland an APEX API for application software.Originally, LithOS was developed as a guest RTOS for the XtratuM Next Generation hypervisor, which enforces strict TSP within a virtualized environment. However, certain embedded applications do not require complex hypervisor-managed partitioning, particularly when strict timing constraints or hardware limitations prevent virtualization. LithOS-BM addresses this by replacing the hypervisor layer with a custom Board Support Package that interfaces directly with the hardware. This approach maintains ARINC 653 compliance, preemptive task scheduling, and temporal isolation while fully controlling the underlying hardware platform as a standalone RTOS.
Miguel Gotor-Ramos, Carlos Cuesta-Martínez, Miguel Masmano-Tello et al.· Jornadas de Automática· 0 citations
Industrial edge platforms increasingly consolidate real-time control and general-purpose workloads on a single system-on-chip (SoC) to reduce costs, power, and complexity. Conventional real-time virtual machine (RTVM) setups, however, typically rely on PREEMPT_RT Linux and commonly reserve at least two CPU cores to isolate real-time tasks from housekeeping, which hinders scalability on resource-constrained edge platforms. This paper investigates whether low-latency Ethernet networking with tight observed tail latency can be sustained in a single-core RTVM configuration. We implement a single-core Zephyr-based RTVM on ACRN and compare it with a single-core PREEMPT_RT Linux RTVM under the same VM topology, using the same directly assigned Intel i226-LM PCIe Ethernet NIC via passthrough and an identical UDP echo workload. Latency measurements across 30 million packets at a traffic rate of 8 thousand packets per second (8 kpps) characterize both averagecase and extreme-tail behavior. PREEMPT_RT Linux shows severe tail amplification even without interference (99.999th percentile: $\mathbf{2 1 6 3} \boldsymbol{\mu} \mathbf{s}$; max: $\mathbf{6 8 7 2} \boldsymbol{\mu} \mathbf{s})$, while Zephyr maintains a tightly concentrated latency distribution (99.999th percentile: $79 \mu \mathrm{s}$; max: $82 \mu \mathrm{s})$. Under full-system noisy-neighbor load, Zephyr preserves sub- $\mathbf{1 0 0}-\boldsymbol{\mu} \mathbf{s}$ observed tail latency, whereas Linux degrades further. These empirical findings provide evidence that a specialized RTOS-based RTVM can sustain tight tail-latency performance and low delay variation on a single core, challenging the conventional two-core provisioning strategy for real-time edge systems.
Chwee-Lin Choong, Yoong Siang Song, Xin Yuan et al.· IEEE International Conferenc...· 0 citations
WebAssembly (WASM) is emerging as a lightweight alternative to containers for Function-as-a-Service (FaaS) across the edge-cloud continuum. However, existing WASM-based serverless platforms are tightly coupled to specific execution engines and predominantly designed for stateless workloads. This clashes with the heterogeneity of edge deployments, which demand support for stateful applications under diverse hardware and workload constraints. We introduce WASP, a configurable framework that brings stateful serverless execution to the edge-cloud continuum. By abandoning monolithic architectures in favor of strictly decoupled, pluggable components, WASP lets system administrators swap the WASM runtime and the datastore to fit available resources and application requirements, without altering application code. Configurable lifecycle and caching policies further enable fine-tuning for diverse non-functional requirements. Our experimental evaluation demonstrates that WASP introduces negligible runtime overhead and, by swapping runtimes, datastores, and policies, exposes radically different memory and latency profiles, confirming its adaptability to the heterogeneous constraints of the edge-cloud continuum.
