As quantum computing continues to demonstrate promise and attract growing attention, there is an increasing need for more precise experiments to advance the development of quantum devices, as well as higher circuit throughput to validate more domain applications. However, this need is hindered by a memory bottleneck at the quantum control system layer, arising from limited on-chip BRAM capacity and the non-deterministic latency of DRAM. To break this bottleneck, we present Ant-Q, a memory hierarchy design that integrates DRAM with BRAM to support pipelined quantum circuit execution while ensuring deterministic inter-circuit timing. We evaluated Ant-Q using 26 real-world experimental and computing circuits. The results show that Ant-Q supports deep circuits for 1Q and 2Q Randomized Benchmarking and reduces the overhead of circuit loading and readout uplink relative to execution time from 22.90%-1417.05% to near zero. Ant-Q is being integrated into QubiC 3.0, with part of its functionalities already available.
This work makes the QuEST state-vector simulator malleable with the Dynamic Management of Resources (DMR) framework, so that a single job resizes between circuits, and evaluates the reconfiguration overhead on MareNostrum 5 and shows that a single job can run a batch of circuits of different sizes, adapting its allocat...
Íñigo Aréjula-Aísa, Sergio Iserte, P. Sandås et al.· 0 citations
Routing-aware pruning is established as a practical and unified compilation strategy across the quantum computing stack and a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates.
Pau Escofet, C. G. Almudéver, S. Abadal et al.· IEEE Transactions on Circuit...· 0 citations
Semiconductor spin qubits offer a promising route to compact and scalable quantum computers, combining long coherence times in isotopically purified silicon with compatibility with semiconductor manufacturing. Beyond computational speedup, their energy efficiency is an important consideration for future large-scale sys...
J. Santos, Jayshankar Nath, Marco Pezzutto et al.· 0 citations
This work shows that the compilation method Parity Twine perfectly complements the hardware's capabilities to perform tasks such as the quantum Fourier transform or QAOA, and describes an error detection technique native to Parity Twine, which EO qubits can leverage in a unique and advantageous way to improve algorithm...
F. Lohof, Florian Ginzel, Wolfgang Lechner· 1 citation
An evolutionary framework in which large language models propose circuit designs and an independent evaluator verifies and scores them is introduced and opens the door for evaluator-guided LLM co-design of new algorithmic structures for quantum computation.
An-Di Gu, Alek H. Kemeny, S. Yelin et al.· 8 citations· ⚡2
Quantum error correction (QEC) relies on repeated parity extraction, mid-circuit measurement (MCM), reset, feed-forward, and scheduling, yet these primitives are usually assessed either in isolation or through resource-demanding experiments. We introduce a few-sample benchmark of QEC-relevant primitives based on an MCM...
J. A. M. K. Michielsen· 0 citations
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