Automated Generation of Software-Based Self-Test From ATPG Patterns Targeting Transition Delay Faults in the Decode Stage of the RISC-V-Based Microcontrollers

Abstract

Software-Based Self-Tests (SBSTs), grouped in Software Test Library, are functional testing approaches used as a flexible solution during manufacturing tests to enhance the quality of outgoing silicon or online testing, as functional safety mechanisms. While SBSTs have proven to be effective for stuck-at fault testing, their development for transition delay fault models (TDFs) remains challenging, requiring skilled test engineers and time-consuming manual efforts. This paper presents a novel methodology for automatically generating SBSTs oriented to test TDF models in the decoder unit of microprocessors by leveraging already generated scan-based test patterns. The proposed approach analyzes scan-based patterns to extract instructions and register file values, processes this data to create code portions that maintain proper timing for TDF excitation and propagation, and handles generated control-flow instructions. The methodology considers pipeline depth to ensure fault visibility in processor registers and includes proper code relocation through linker scripts. The generated SBST can serve as input for further optimization through genetic or ATPG-driven methods to enhance fault detection capabilities or optimize characteristics such as code size and execution time. Experimental validation is conducted on open-source RISC-V CPU cores such as CV32E40P from the Open Hardware group, the Berkeley Out-of-Order Machine (BOOM), and Rocket core from UCBerkley, synthesized using a 45nm technology library. Experimental results are primarily aiming at maximizing the TDF coverage on the decode unit of the CPUs, since a fault in the decode unit may affect the entire behavior of the CPUs. Afterward, the generated SBST is fault graded on the entire datapath logic of all the CPUs. The experimental results demonstrate the effectiveness of transforming scan-based test patterns into correct functional tests while having moderate fault detection capabilities with low manual efforts compared to manually developed SBSTs.