Designing and Building an FPGA Accelerator That Uses Less Energy for DNN Inference

Abstract

Deep Neural Networks (DNNs) are critical to modern AI applications, yet their deployment on standard CPUs and GPUs is constrained by high power consumption and computational latency, particularly in resource-constrained edge environments. To address these limitations, this paper presents the design and implementation of an energy-efficient FPGA hardware accelerator tailored for DNN inference. The proposed architecture optimizes matrix multiplication through a combination of parallel processing elements, pipelined data flows, weight quantization, and on-chip memory reuse strategies, minimizing off-chip memory access overhead. Developed using hardware description language (HDL) and deployed on an AMD Artix-7 FPGA platform, the design was evaluated against standard CPU and GPU baselines across throughput, latency, resource utilization, and power consumption metrics. Experimental results demonstrate that the accelerator achieves superior energy efficiency and reduced latency while maintaining competitive inference accuracy. Furthermore, the scalable architecture accommodates deeper network topologies without proportional power escalation. This research establishes a viable foundation for sustainable, realtime edge AI deployment and hardware-driven neural network optimization.