Compute-in-memory (CiM) offers a promising solution to the hardware challenges faced in artificial intelligence (AI) and the Internet of Things (IoT), particularly in tackling the ”memory wall” problem. By leveraging nonvolatile memory (NVM) devices arranged in a crossbar structure, CiM efficiently accelerates multiply-accumulate (MAC) computations, which are essential for neural networks and various AI models. Emerging NVM, i.e., Ferroelectric FET (FeFET), is a particularly appealing choice for constructing ultra-low-power CiM arrays due to its CMOS compatibility, voltage-driven write/read mechanisms and high ION/IOFF ratio. Operating FeFETs in the subthreshold region, i.e., subthreshold-FeFETs, further reduces power, but introduces vulnerability to temperature drift, leading to potential accuracy degradation. In this paper, we present subthreshold-FeFET based temperature-resilient 2T-1FeFET and 2FeFET-1T CiM cell designs that address the temperature vulnerability. These two cells leverage feedback mechanisms to minimize the output current fluctuations caused by temperature drift. We further propose GTRCiM, a novel generic temperature-resilient CiM design that accommodates both our proposed CiM cells and other typical FeFET based cells while maintaining ultra-low-power consumption with subthreshold-FeFETs. By incorporating an additional column of the CiM array as a reference, and leveraging the temperature-resilient cell design, GTRCiM compensates for the effects of temperature drift, as temperature affects both arrays uniformly. We integrate the proposed GTRCiM array with typical 1FeFET-1R, and our proposed 2T-1FeFET, 2FeFET-1T cells and validate that GTRCiM enhances the temperature resilience with our proposed cells and even the temperature vulnerable 1FeFET-1R cell. Benchmarking results at system level using the NeuroSim framework show that our proposed GTRCiM array integrated with subthreshold-FeFET based 1FeFET-1R cells achieves 28.09 TOPS/W energy efficiency, surpassing existing CiM designs while maintaining sufficient temperature resilience.
Yifei Zhou, Zeyu Yang, Meimei Ma et al.· ACM Transactions on Design A...· 0 citations
The first systematic study of imperfect specifications is presented and an automated framework to repair them to enhance the quality of resulting Verilog design is proposed, demonstrating the capabilities of specification repair by {VClare} as well as further potential of LLMs in front-end hardware design.
Zhuorui Zhao, Bing Li, Yu Li et al.· arXiv.org· 0 citations
Seer is proposed, a training-free framework that detects their valid semantic boundary using a Signal-to-Noise Ratio (SNR)-based criterion and performs one-shot truncation of the redundant suffix for all subsequent computations, offering a highly efficient, plug-and-play solution for DMLLM acceleration.
Qicheng Zhao, Qi Sun, Zheyu Yan· 7 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.