Open access
Aug 2026
A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout
The architecture thereby combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation, and combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation.
Ao-Ming Zhan, Ye Zhao, Yu-Mei Zhou et al.
· Applied Sciences · 0 citations