A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

Design And Implementation Of An ADC/DAC-Free Walsh-Hadamard Transform Based Neural Network Accelerator Using Bit-Plane Processing

An ADC/DAC-free neural accelerator based on the Walsh-Hadamard Transform and bit-plane processing that offers a multiplier-free, converter-free, regular, and scalable solution for low-power edge intelligence.

You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors

Analog Computing-in-Memory (ACiM) accelerates deep neural networks by keeping weights inside memory arrays and executing dot products in the analog domain. However, modern ACiM accelerators are often limited by the"ADC wall": analog-to-digital converters consume a large fraction of energy and area, while bit-sliced execution repeatedly invokes these converters. Existing designs reduce this cost with low-resolution readout or time multiplexing, but they either lose output fidelity or introduce serialization overhead. Charge-CIM addresses this bottleneck by using switched-capacitor charge redistribution as a unified computing and conversion substrate. The same capacitor fabric performs input conversion, analog MAC, weighted shift-and-add, and readout quantization, reducing both standalone converter overhead and intermediate ADC invocations. A differential readout path further combines paired partial sums during ADC quantization, providing a highly compact and energy-efficient solution for array integration. With dataflow architecture support, we evaluated Charge-CIM on a suite of DNN benchmarks, from CNNs to Transformer models, and experimental results show that Charge-CIM reduces ADC energy by 91.7% under our evaluation setup and improves energy efficiency by 2.7x and throughput by 2.0x compared to the state-of-the-art charge-domain CIM accelerator.

Transformer Accelerator (TFA): A Macro-Op INT8 Hardware Chip for Transformer Inference and Machine Translation

We present the Transformer Accelerator (TFA), a synthesizable, parameterizable INT8 memory-to-memory engine for transformer inference. One time-multiplexed datapath handles prompt processing and autoregressive generation. TFA implements matrix multiplication, softmax, RMSNorm, elementwise, and copy/gather operations through eight 512-bit macro-op descriptors. Offline-compiled programs are fetched, validated, and dispatched through AXI interfaces, supporting encoder, decoder, and encoder-decoder models. The RTL combines an output-stationary multiply-accumulate array with ping-pong buffers that overlap DMA and compute, bit-exact reciprocal-square-root and divide units, key-value-cache and embedding addressing, and an abort-safe zero-padding write engine. A UVM environment byte-compares outputs against a bit-exact golden model. Across 25 tests and 34 constrained-random runs, TFA achieved zero mismatches, 100% functional coverage, and 94.96% code coverage. We compiled the t5-small encoder-decoder pipeline for English-to-French, German, and Romanian translation. On ten multilingual proverbs, TFA executed 70,320 descriptors and matched 37.9 MB of golden-model output with zero mismatches. INT8 output matched the floating-point reference token-for-token on five sentences; the rest produced valid alternative translations. Randomized-Hadamard reparameterization recovered about 11 dB of per-tensor INT8 signal-to-noise ratio across layers. The verification configuration achieved about 20x end-to-end speedup over a 22-thread CPU, while larger designs are projected to reduce energy per token by about 1000x. After RAM inference recoding, logic area fell to 2.73 mm2, and the design completed design-rule-clean synthesis and place-and-route on SkyWater sky130. TFA demonstrates end-to-end, bit-exact execution of pretrained transformers using compact hardware and compiler-managed quantization.

CDCA: a column-serial and dual-engine collaborative accelerator for depthwise separable convolution

Radix-4 carry-save adder based accumulator for high-performance MAC units in factored systolic array accelerators

Abstract Machine learning workloads impose extreme computational demands on hardware, driving the adoption of domain-specific accelerators built around Systolic Arrays (SAs). Factored Systolic Arrays (FSAs) based on Radix-8 Booth multiplications reduce multiplier complexity by relocating the encoding logic to the array periphery, thereby simplifying each Processing Element (PE). Despite this multiplier-side enhancement, the Multiply-Accumulate (MAC) unit’s accumulation stage continues to impose a critical bottleneck when implemented with a standard Ripple Carry Adder (RCA), whose carry-propagation delay scales linearly with the accumulator width. This paper presents a Radix-4 Carry-Save Adder (CSA) accumulator within the Radix-8 FSA MAC and evaluates it on the Xilinx Spartan-3E FPGA design suite 14.7. The proposed architecture significantly achieves 22.5%, 21.3%, 24.5% and 4.3% reductions in critical-path delay, LUT, Slice utilization and Power consumption relative to the RCA baseline. Further, as approximate computing has emerged as a promising solution for enhanced efficiency, a lower-part OR Adder variant is evaluated, achieving the best power-delay product (2204 pJ). Optimization within FSA MACs enables high-throughput Machine Learning acceleration.

DTX: A Throughput-First Training Accelerator for Diffusion and Transformer Models

DTX is a throughput-first training accelerator for diffusion and transformer models. Any summation serialized through a single FP32 adder is a loop-carried dependence that pins a machine near 2 FLOP/cycle regardless of physical design; DTX is built so no such chain exists anywhere -- every reduction is a pipelined binary tree, every FP operator a two-stage pipeline with initiation interval 1. An 8x8 weight-stationary systolic array with a fused bias/activation/cast epilogue, an 8-lane vector unit, an 8-lane fused AdamW pipeline, and a pipelined Philox Gaussian source are co-issued by a 4-slot VLIW word over a unified 64 KB tile space: 216 FLOP/cycle, roughly 108x the loop-carried floor per clock. With no canonical sum order, verification is tolerance-based against an FP64 golden model, with exact-equality carve-outs and a demonstrably tight bound (a premise-violating program measured 5,340x over budget; 17/17 tests, 107,108 elements, zero failures). Semantic gates confirm an on-device diffusion-MLP run reduces its loss (56.4 to 26.0), counter-level proof shows compute/DMA overlap sustains the peak, an analytical iso-node decomposition bounds the GPU comparison at 6-10x throughput per watt, and a sky130 campaign hardens the systolic array to DRC-clean GDS at 83.3 MHz post-route -- 1.9x an optimized loop-carried MAC baseline on the same node and flow.