Author

Shashank Chaurasia

2 papers indexed here

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Review Sep 2026

Verification Reward Model for Reinforcement Learning in Chip Design Verification

A Verification Reward Model framework for training language models to create and repair chip verification artifacts, with full UVM capability admitted through feature-specific qualification, and a first experiment on a small, open-tool-compatible benchmark with lightweight models is described.

Shashank Chaurasia · 0 citations

Preprint Sep 2026

The World Model Hardware Accelerator

WMHA is exploited in WMHA, a latency-first diffusion-transformer inference accelerator: a very-long-instruction-word sequencer issues four engines from one instruction word, a weight-stationary 16x16 dual-dot array streams FP8 and BF16 contractions, and a single-pass online-softmax attention pipeline keeps keys and val...

Shashank Chaurasia · 0 citations