This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.
Yang Chen, Daniele Storelli, Xin-Yi Zhao et al.· 0 citations
Conventional computing architectures are reaching their scalability limits, while their energy demands increase rapidly. A bottleneck is the separation of memory and processing units, which requires a continuous data transfer. This memory wall increases the power consumption and limits the processing speed at the same time. Computing-in-Memory (CIM) has emerged as an alternative computing paradigm, where the data is processed directly within the memory array, thereby reducing data transfer costs. Emerging non-volatile devices such as magnetic-tunnel junctions (MTJ), phase-change memory (PCM), or resistive random-access memory (RRAM) are promising candidates for CIM. As re-programmable and highly scalable devices, they combine both computing and memory functionalities. While the feasibility of RRAM-based CIM has been proven, both in simulation and in experimental demonstrations, the operational reliability is still an ongoing issue. In this work, we demonstrate the parallel and cascading execution of logic functions in an RRAM-based CIM array. The experimental results are complemented by an in-depth simulation study to investigate the logic accuracy and optimization strategies. These results provide new insights into the reliability and logic correctness of resistive CIM and outline a potential path towards scalable and energy-efficient computing architectures.
L. Brackmann, Tobias Ziegler, N. Kopperberg et al.· npj Unconventional Computing· 0 citations
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