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RENZ HERALD ELAMPARO

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#reinforcement learning Open access Oct 2026

LLM-Driven Verilog Generation and Verification for RISC-V Processor Design

Large language models (LLMs) are increasingly used in Electronic Design Automation (EDA) to write hardware description code. This paper reviews how LLMs generate and verify Verilog for a RISC-V processor datapath, a core topic in Computer Architecture and Organization. The review is built around the AI-driven logic syn...

RENZ HERALD ELAMPARO · 0 citations
#large language models Open access Oct 2026

LLM-Driven Verilog Generation and Verification for RISC-V Processor Design

Large language models (LLMs) are increasingly used in Electronic Design Automation (EDA) to write hardware description code. This paper reviews how LLMs generate and verify Verilog for a RISC-V processor datapath, a core topic in Computer Architecture and Organization. The review is built around the AI-driven logic syn...

RENZ HERALD ELAMPARO · 0 citations

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