Reliability challenges for resistive random-access memory-based parallel logic computing
Conventional computing architectures are reaching their scalability limits, while their energy demands increase rapidly. A bottleneck is the separation of memory and processing units, which requires a continuous data transfer. This memory wall increases the power consumption and limits the processing speed at the same time. Computing-in-Memory (CIM) has emerged as an alternative computing paradigm, where the data is processed directly within the memory array, thereby reducing data transfer costs. Emerging non-volatile devices such as magnetic-tunnel junctions (MTJ), phase-change memory (PCM), or resistive random-access memory (RRAM) are promising candidates for CIM. As re-programmable and highly scalable devices, they combine both computing and memory functionalities. While the feasibility of RRAM-based CIM has been proven, both in simulation and in experimental demonstrations, the operational reliability is still an ongoing issue. In this work, we demonstrate the parallel and cascading execution of logic functions in an RRAM-based CIM array. The experimental results are complemented by an in-depth simulation study to investigate the logic accuracy and optimization strategies. These results provide new insights into the reliability and logic correctness of resistive CIM and outline a potential path towards scalable and energy-efficient computing architectures.