Owing to increased power density with each newer technology node, transistors suffer from increased Self-Heating (SH) at room temperature, which is a daunting challenge for circuits and processors’ reliability. Given the increasing interest in leveraging cryogenic temperatures to enhance the performance and energy efficiency of computing systems, understanding SH effects at cryogenic temperatures is critical for the reliability and optimization of such systems. This work presents a comprehensive investigation of SH effects from the transistor to the processor level on the advanced 5 nm FinFET node under cryogenic conditions, specifically at 77 K. Further, it presents a pioneering comparison of SH effects between 5 nm FinFET and 28 nm FDSOI transistors at 77 K. Our findings reveal that FinFET devices on bulk substrate, despite their 3D-confined structure and reduced scale to extreme 5 nm, exhibit better thermal characteristics compared to FDSOI devices at 77 K. This is primarily attributed to the inherent design of FDSOI devices, where the buried oxide layer acts as a thermal barrier, thereby significantly restricting heat dissipation. Further, we explore the standard cell libraries and a processor core operating at 77 K with and without i) SH effect and ii) scaled parasitic resistance using 5 nm FinFETs. The exploration undertaken in this study not only demystifies the thermal behavior of a cutting-edge 5 nm technology under extremely low temperatures but also establishes a new paradigm in selecting technologies for future high-performance computing applications at cryogenic temperatures. It opens new avenues for the development of more efficient and reliable computing systems, paving the way for future innovations in cryogenic computing.
S. S. Parihar, F. Klemme, Anirban Kar et al.· IEEE transactions on compute...· 0 citations
Compute-in-memory (CiM) offers a promising solution to the hardware challenges faced in artificial intelligence (AI) and the Internet of Things (IoT), particularly in tackling the ”memory wall” problem. By leveraging nonvolatile memory (NVM) devices arranged in a crossbar structure, CiM efficiently accelerates multiply-accumulate (MAC) computations, which are essential for neural networks and various AI models. Emerging NVM, i.e., Ferroelectric FET (FeFET), is a particularly appealing choice for constructing ultra-low-power CiM arrays due to its CMOS compatibility, voltage-driven write/read mechanisms and high ION/IOFF ratio. Operating FeFETs in the subthreshold region, i.e., subthreshold-FeFETs, further reduces power, but introduces vulnerability to temperature drift, leading to potential accuracy degradation. In this paper, we present subthreshold-FeFET based temperature-resilient 2T-1FeFET and 2FeFET-1T CiM cell designs that address the temperature vulnerability. These two cells leverage feedback mechanisms to minimize the output current fluctuations caused by temperature drift. We further propose GTRCiM, a novel generic temperature-resilient CiM design that accommodates both our proposed CiM cells and other typical FeFET based cells while maintaining ultra-low-power consumption with subthreshold-FeFETs. By incorporating an additional column of the CiM array as a reference, and leveraging the temperature-resilient cell design, GTRCiM compensates for the effects of temperature drift, as temperature affects both arrays uniformly. We integrate the proposed GTRCiM array with typical 1FeFET-1R, and our proposed 2T-1FeFET, 2FeFET-1T cells and validate that GTRCiM enhances the temperature resilience with our proposed cells and even the temperature vulnerable 1FeFET-1R cell. Benchmarking results at system level using the NeuroSim framework show that our proposed GTRCiM array integrated with subthreshold-FeFET based 1FeFET-1R cells achieves 28.09 TOPS/W energy efficiency, surpassing existing CiM designs while maintaining sufficient temperature resilience.
Yifei Zhou, Zeyu Yang, Meimei Ma et al.· ACM Transactions on Design A...· 0 citations
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