4 papers indexed here
We haven’t gathered this author’s papers yet. Follow them and we’ll fetch their work.
Not the right person? Other researchers publish under this name.
This work proposes CCHPC1.1, an arbitrary-order masked gadget construction that improves Constant-Cycle Hardware Private Circuits (CCHPC) while preserving security in the Robust but Relaxed (RR) d-probing model and under the Probe- Isolating Non-Interference (PINI) composability notion.
With the widespread adoption of Field Programmable Gate Arrays (FPGAs) in security-critical industries such as defense and telecommunications, ensuring the confidentiality of sensitive data processed by these devices has become paramount. Side-Channel Analysis (SCA) poses a significant threat, necessitating the protect...
This work focuses on detecting (low-level) vulnerabilities in masked FPGA designs through experimental and tool-assisted evaluation and shows how to formally abstract, unveil, and mitigate such leakages, thereby enabling a security-aware FPGA design flow that spans from the behavioral to the physical level.
HPCC is presented, the first low-latency 3-input multiplication gadget for arbitrary fields that maintains a constant latency of one cycle, independent of the number of shares, and is leveraged to implement the first composable AES S-Box with two cycles of latency with an arbitrary number of shares.
We use cookies to run the site and, with your consent, for analytics and to show ads. See our Cookie Policy.
