Skip to content
Review Open access

From Cray to Exascale: A Critical Survey of Supercomputer Architecture Evolution, Heterogeneity, and Interconnect Bottlenecks

Aug 2026 · International Journal of Computer Science and Mathematical Theory · pp. 97 · 0 citations

TL;DR

A critical survey of supercomputer architecture from early vector machines to contemporary exascale systems, with particular emphasis on three persistent challenges: memory hierarchy design, interconnection network scalability, and thermal management.

Abstract

The evolution of supercomputer architecture has undergone several transformative phases since the 1960s, yet existing surveys have not adequately captured the engineering trade-offs that defined each generation. This paper presents a critical survey of supercomputer architecture from early vector machines to contemporary exascale systems, with particular emphasis on three persistent challenges: memory hierarchy design, interconnection network scalability, and thermal management. Drawing on foundational work by Cray and subsequent massively parallel systems, we examine how the transition from shared memory to distributed architectures enabled processor counts to grow from dozens to millions. The paper analyses recent exascale systems including Frontier, Fugaku, and LUMI, alongside emerging accelerator technologies such as GPU-based nodes, wafer-scale integration, and specialized interconnects including Slingshot, InfiniBand, and Omni-Path. Our survey identifies that while peak performance has grown exponentially, the gap between theoretical and sustained performance remains significant, largely due to interconnect latency and memory bandwidth limitations. We further evaluate contemporary cooling approaches from immersion to direct to-chip liquid systems, noting that power density has emerged as the primary constraint on further scaling. Building upon earlier work by Oraye and Anireh (2022), this survey provides updated taxonomies and performance metrics that inform future exascale and post-exascale designs.

Read PDF

Similar papers

Book Open access Sep 2026

Wavel: A Fast and Efficient Compilation System for Wafer-Scale Accelerators

Wavel is presented, a fast and efficient compilation system for wafer-scale accelerators that introduces MeshIR to make executable schedules explicit, constructs them through two legal locality-preserving primitives, CUT and TUNE, and uses physical cost evaluation with structured pruning to keep search practical.

Ye-Qi Huang, Cong-Jie He, Hao-Cheng Xiao et al. · 0 citations
Sep 2026

LineShine: online acceleration for HPC-AI converged scientific computing

LineShine is presented, a newly deployed exascale supercomputer whose online acceleration architecture provides a new design point for converged HPC and AI and demonstrates that its balanced architecture and software stack can translate system capability into high throughput, robust scalability, and sustained scientifi...

Yu-Tong Lu, Guang-Nan Feng, Hao-Huan Fu · 2 citations
Review Aug 2026

AI Hardware Accelerators for Large Language Models: Architectures and the Memory Wall

This review surveys the full landscape of AI hardware accelerators for LLMs, including general-purpose GPUs, custom ASICs, reconfigurable FPGAs, processing-in-memory and near-memory architectures, and emerging neuromorphic and photonic approaches across cloud and edge deployment.

Siddharth Patel, Rohit Singh · 0 citations
Preprint Aug 2026

To Scale Up or To Scale Out: Evaluating Space-Time Costs of Compiled Logical Circuits on Modular Superconducting Quantum Processors

Modular integration has emerged as the main pathway for scaling superconducting quantum processing units (QPUs) beyond the constraints of fabrication yield and physical footprint. Currently, two primary strategies lead this effort. Mirroring the"Scaling Up"and"Scaling Out"approaches in GPU architectures and AI infrastr...

Nikiforos Paraskevopoulos, S. de Bone, Mick Christophersen et al. · 0 citations

Procyon: Promoting Fine-Grain Multi-Tenancy to Optimize Sparse Streaming Accelerators

Procyon, a fine-grain multi-tenancy framework that fuses the PE instruction streams of multiple workloads into a unified execution schedule, substantially reduces PE underutilization that results in 3 × speedup over state-of-the-art sparse streaming accelerators, and reaches a peak throughput of 61 .

Ubaid Bakhtiar, Jeremy Sha, Helya Hosseini et al. · 0 citations
Open access Oct 2026

Demystifying SpMV Performance: Bottleneck Characterization and Open Challenges

Sparse Matrix-Vector Multiplication (SpMV) is a critical computational kernel in scientific computing, graph processing, and machine learning. Despite its importance, SpMV achieves only a small fraction of peak performance, varying substantially across matrices and architectures. This paper comprehensively analyzes SpM...

Panagiotis Mpakos, Dimitrios Galanopoulos, Petros Anastasiadis et al. · 0 citations

We use cookies to run the site and, with your consent, for analytics and to show ads. See our Cookie Policy.