Aug 2026· International Journal of Computer Science and Mathematical Theory· pp. 97· 0 citations
TL;DR
A critical survey of supercomputer architecture from early vector machines to contemporary exascale systems, with particular emphasis on three persistent challenges: memory hierarchy design, interconnection network scalability, and thermal management.
Abstract
The evolution of supercomputer architecture has undergone several transformative phases
since the 1960s, yet existing surveys have not adequately captured the engineering trade-offs
that defined each generation. This paper presents a critical survey of supercomputer
architecture from early vector machines to contemporary exascale systems, with particular
emphasis on three persistent challenges: memory hierarchy design, interconnection network
scalability, and thermal management. Drawing on foundational work by Cray and subsequent
massively parallel systems, we examine how the transition from shared memory to distributed
architectures enabled processor counts to grow from dozens to millions. The paper analyses
recent exascale systems including Frontier, Fugaku, and LUMI, alongside emerging
accelerator technologies such as GPU-based nodes, wafer-scale integration, and specialized
interconnects including Slingshot, InfiniBand, and Omni-Path. Our survey identifies that while
peak performance has grown exponentially, the gap between theoretical and sustained
performance remains significant, largely due to interconnect latency and memory bandwidth
limitations. We further evaluate contemporary cooling approaches from immersion to direct
to-chip liquid systems, noting that power density has emerged as the primary constraint on
further scaling. Building upon earlier work by Oraye and Anireh (2022), this survey provides
updated taxonomies and performance metrics that inform future exascale and post-exascale
designs.
Wavel is presented, a fast and efficient compilation system for wafer-scale accelerators that introduces MeshIR to make executable schedules explicit, constructs them through two legal locality-preserving primitives, CUT and TUNE, and uses physical cost evaluation with structured pruning to keep search practical.
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LineShine is presented, a newly deployed exascale supercomputer whose online acceleration architecture provides a new design point for converged HPC and AI and demonstrates that its balanced architecture and software stack can translate system capability into high throughput, robust scalability, and sustained scientifi...
This review surveys the full landscape of AI hardware accelerators for LLMs, including general-purpose GPUs, custom ASICs, reconfigurable FPGAs, processing-in-memory and near-memory architectures, and emerging neuromorphic and photonic approaches across cloud and edge deployment.
Modular integration has emerged as the main pathway for scaling superconducting quantum processing units (QPUs) beyond the constraints of fabrication yield and physical footprint. Currently, two primary strategies lead this effort. Mirroring the"Scaling Up"and"Scaling Out"approaches in GPU architectures and AI infrastr...
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Procyon, a fine-grain multi-tenancy framework that fuses the PE instruction streams of multiple workloads into a unified execution schedule, substantially reduces PE underutilization that results in 3 × speedup over state-of-the-art sparse streaming accelerators, and reaches a peak throughput of 61 .
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Sparse Matrix-Vector Multiplication (SpMV) is a critical computational kernel in scientific computing, graph processing, and machine learning. Despite its importance, SpMV achieves only a small fraction of peak performance, varying substantially across matrices and architectures. This paper comprehensively analyzes SpM...
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